VHDL
A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration
This article provides a comprehensive methodology that highlights the best practices for mixed-language design integra…
Verilog
Verilog
Verilog2C++
Verilog2C++ is a Verilog to C++ translation program that translates a C++ class of a Verilog design using a cycle-ac…
Verilog
Source Navigator for Verilog
Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many Verilog…
Verilog
Verilog and Specman 'e' Interview Questions
Question 1: Write a verilog assertion for the property that vector S of length 8 is always of even parity and the Hammi…
XVGA
Simple XVGA (1024x768) Controller in Verilog
module xvga(clk,hcount,vcount,hsync,vsync); input clk; // 64.8 Mhz output [10:0] hcount; output [9:0] vcount; …
Verilog
Digital "Greatest Common Divisor (GCD)" - Euclid’s algorithm
Updated on 25th Jan 2022!! The Euclidean algorithm is a method for finding the greatest common divisor (GCD) of two or …
Verilog
Digital "Square root" Computation of a number
By Popular Demand! module sqrt (clk,data,start,answer,done); input clk,start; input [7:0] data; output [3:0] answer;…
Verilog
Verilog - Multiplication Gotcha, did you ever know?!
Did you know this basic gotcha of verilog :-) ? You can use the "*" operator to multiply two numbers: wire […
VHDL Coding Guidelines
HDL Coding Guidelines - Part 1
Coding of circuit behavior and architecture is one of the most critical steps in the whole chip development project. It…
Verilog Tutorial
Comprehensive Verilog Tutorials
The Hyper-links will be updated when the Chapter-wise Tutorials are complete! Your comments, feedback & suggestions…
VHDL
Comparison of VHDL to Other Hardware Description Languages
VHDL Disadvantages VHDL is verbose, complicated and confusing Many different ways of saying the same thing Constructs t…
Verilog
Verilog rules that can save your breath !
This article contains some thoughts of mine about how and engineer should write Verilog code for Synthesis, general rul…
Verilog
Verilog Awareness
Differentiate between Inter assignment Delay and Inertial Delay ? What are the different State machine Styles ? Which i…
Verilog
Verilog Awareness
Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ? What is the difference between bl…
Verilog
Verilog Blocking Vs Non Blocking, Myths and Facts
I know people who swear by blocking and some who swear by non-blocking. So here are some thoughts. There is very little…