Last 2 weeks has witnessed a sudden surge in visitors and so i decided
to continue my experiments for some more time with some new
information or updates on some old articles.
I will try to make some time to answer your questions and queries.
Thanks
Updates
Written by
Tuesday, March 07, 2006
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Another Question:
ReplyDeleteMimic an infinite width register in which the content is input serially LSB first. The output of the register system should indicate whether the present contents of the infinite width register is divisble by 5 or not.
(If it were MSB first, I could use the concept of a state for each remainder, but in this case, that doesn't seem to be possible :( )
Example Inputs and Outputs:
Inputs are assumed valid at every positive clock edge.
0 -> 0
00 -> 1
100 -> 1
1100 -> 0
01100 -> 0
001100 -> 1
1001100 -> 0
and so on...
I would also like to some pointers on multi-clock domain designs. I think they are not covered in any standard textbooks also...
ReplyDelete.Suppose you have a combo ckt b/w two registers driven by a
ReplyDeleteclock.If the delay of Combo ckt is larger than the clock period,
then how would you overcome the problem?
.Suppose you have a combo ckt b/w two registers driven by a
ReplyDeleteclock.If the delay of Combo ckt is larger than the clock period,
then how would you overcome the problem?
answers @ grumpytom.com
ReplyDelete