Updates


Last 2 weeks has witnessed a sudden surge in visitors and so i decided
to continue my experiments for some more time with some new
information or updates on some old articles.

I will try to make some time to answer your questions and queries.

Thanks


{ 6 Reactions ... read them below or write one }

Anonymous said on March 8, 2006 at 7:17 AM

Another Question:

Mimic an infinite width register in which the content is input serially LSB first. The output of the register system should indicate whether the present contents of the infinite width register is divisble by 5 or not.

(If it were MSB first, I could use the concept of a state for each remainder, but in this case, that doesn't seem to be possible :( )

Example Inputs and Outputs:

Inputs are assumed valid at every positive clock edge.

0 -> 0
00 -> 1
100 -> 1
1100 -> 0
01100 -> 0
001100 -> 1
1001100 -> 0

and so on...

Anonymous said on March 11, 2006 at 6:34 AM

I would also like to some pointers on multi-clock domain designs. I think they are not covered in any standard textbooks also...

vijayakumar said on May 31, 2006 at 6:52 PM

Hi

Please continue your good work,, It will be useful to starters like me

Thanks

Anonymous said on August 11, 2006 at 11:12 PM

.Suppose you have a combo ckt b/w two registers driven by a
clock.If the delay of Combo ckt is larger than the clock period,
then how would you overcome the problem?

Anonymous said on August 11, 2006 at 11:13 PM

.Suppose you have a combo ckt b/w two registers driven by a
clock.If the delay of Combo ckt is larger than the clock period,
then how would you overcome the problem?

Anonymous said on September 1, 2006 at 9:06 PM

answers @ grumpytom.com

Post a Comment

Your comments will be moderated before it can appear here.