DSP is replacing much of the analog signal processing inside high-speed SerDes because, at 100 Gb/s per lane and above with PAM4 signalling, it is easier to digitise the received signal with a fast ADC and equalise it in digital logic than to do the same work with analog circuits. Digital equalisers scale with each new process node, can be made much longer and more flexible, and behave the same across process, voltage and temperature. Analog does not disappear: the transmitter driver, the front-end amplifier and continuous-time equaliser, the ADC itself and the clocking all remain analog, and they are harder to design than ever.
In this video, the CEO of Alphawave IP (Alphawave Semi) covers the benefits of DSP-based SerDes, which have become more popular since standards started to converge on PAM4 signalling and semiconductor manufacturing processes have continued to improve. The notes below give the background needed to follow the discussion.
Key takeaways
- A SerDes (serialiser/deserialiser) moves data over a single differential pair at very high rates; the receiver must undo the loss and reflections of the channel.
- PAM4 carries two bits per symbol, halving the symbol rate compared with NRZ, but each of its three eyes is about one third of the NRZ eye height, a penalty of roughly 9.5 dB.
- A DSP-based receiver samples the signal with a time-interleaved ADC and performs equalisation, detection and clock recovery in digital logic.
- Digital equalisers can use many taps and advanced detectors such as maximum likelihood sequence detection, which are impractical in analog at these speeds.
- The trade-offs are power, area and latency, which is why analog-style SerDes still compete on short, low-loss links.
Why the analog approach ran out of room
From NRZ to PAM4
NRZ sends one bit per symbol on two levels. To double the data rate, you double the symbol rate, which doubles the Nyquist frequency and greatly increases channel loss. PAM4 uses four levels to send two bits per symbol, so a 100 Gb/s class lane runs at about 53 GBd rather than over 100 GBd. The cost is signal-to-noise ratio: the three stacked eyes are each about one third the height of a single NRZ eye, so 20 log10(3), about 9.5 dB, is lost before the channel does any damage. Standards such as IEEE 802.3ck (100 Gb/s per lane electrical Ethernet), OIF CEI-112G and PCIe 6.0 (64 GT/s) all moved to PAM4, and that convergence is what made DSP receivers worth the investment.
Equalisation at very short unit intervals
Classic analog receivers combine a continuous-time linear equaliser (CTLE) with a decision feedback equaliser (DFE). A DFE subtracts the echo of past symbols from the current one, but it must decide on a symbol, scale it and feed it back within one unit interval. At 53.125 GBd, one unit interval is about 18.8 ps. Designers get around this with speculative (loop-unrolled) DFEs, but for PAM4 a single unrolled tap needs a set of three slicers for each of the four possible previous symbols, twelve comparators in all, and the count grows quickly with more taps. Long, lossy channels need more correction than a handful of analog taps can give.
What process scaling favours
Each FinFET or gate-all-around node makes digital logic smaller and lower in energy per operation, while analog circuits gain far less, because lower supply voltages and device mismatch eat into their headroom. Once the ADC is fast and accurate enough, moving the equaliser into digital logic lets the receiver ride the same scaling curve as the rest of the chip.
How a DSP-based SerDes receiver works
- Analog front end. A termination network, a variable gain amplifier and a CTLE set the signal level and remove part of the high-frequency loss.
- ADC. A time-interleaved ADC, often around six to eight bits, samples at the symbol rate. Many slower sub-ADCs run in parallel with staggered clocks.
- Feed-forward equaliser (FFE). A digital FIR filter with many taps cancels pre-cursor and post-cursor inter-symbol interference.
- DFE or sequence detector. A short digital DFE, or a maximum likelihood sequence detector on harder channels, makes the symbol decisions.
- Clock and data recovery. Timing error is estimated digitally and steers the sampling clock phase.
- Adaptation and diagnostics. Tap weights adapt continuously, and the DSP can report on-chip eye data, signal-to-noise ratio and pre-FEC error rates, which helps a great deal in link bring-up.
Forward error correction then cleans up the remaining errors. 100G-per-lane Ethernet relies on Reed-Solomon FEC, and PCIe 6.0 added a lightweight FEC with its FLIT mode, so the receiver only needs to reach a raw bit error rate that the FEC can correct rather than an error-free link on its own.
A worked example (illustrative numbers)
Take one 106.25 Gb/s PAM4 lane at 53.125 GBd, sampled by a 7-bit ADC at one sample per symbol.
| Quantity | Calculation | Result |
|---|---|---|
| Unit interval | 1 / 53.125 GHz | about 18.8 ps |
| Nyquist frequency | 53.125 / 2 | about 26.6 GHz |
| Raw ADC output | 53.125 GS/s x 7 bits | about 372 Gb/s per lane |
| Sub-ADC rate with 64-way interleaving | 53.125 / 64 | about 830 MS/s each |
| DSP clock with 64 parallel samples | same as above | about 830 MHz |
The numbers show the shape of the problem. The digital side handles several times the line rate in raw samples, but it does so with wide, parallel logic at under 1 GHz, which suits a modern standard-cell flow. The hard analog work concentrates in the ADC and its clock: matching 64 interleaved sub-ADCs in gain, offset and timing, with sampling-clock jitter that must stay well below 100 femtoseconds rms at these rates.
Analog versus DSP SerDes at a glance
| Aspect | Analog-style receiver | DSP-based receiver |
|---|---|---|
| Equaliser | CTLE plus a few analog DFE taps | CTLE plus long digital FFE, DFE or MLSD |
| Channel reach | Good on short and medium loss | Best on long, lossy, reflective channels |
| Power and area | Lower on easy channels | Higher fixed cost for ADC and DSP |
| Latency | Lower | Higher, from parallel DSP pipelines |
| Process scaling | Limited gains per node | Gains with each digital node |
| Robustness and debug | Sensitive to process, voltage and temperature | Adaptive, with rich on-chip diagnostics |
Where analog still wins
The title is deliberately provocative. Short-reach die-to-die links in chiplet packages, for example those built to UCIe, use simple wide parallel interfaces with little or no equalisation, because a DSP receiver would cost too much power per bit over a few millimetres. In optical modules there is also a counter-trend: linear pluggable optics remove the DSP from the module and rely on the host SerDes to equalise the whole path, trading reach and margin for lower module power. And every DSP SerDes still depends on excellent analog design in its driver, front end, ADC and phase-locked loops. What has changed is where the analog effort goes, not whether it is needed.
Common misconceptions
- "DSP SerDes are all digital." The ADC, clocking and front end are some of the most demanding analog blocks on the chip.
- "PAM4 doubles bandwidth for free." It halves the symbol rate but costs about 9.5 dB of SNR and adds sensitivity to level spacing and non-linearity.
- "DSP is always better." On short, clean channels an analog receiver can meet the error-rate target at lower power and latency.
FAQ
What does DSP-based SerDes mean?
It is a SerDes whose receiver digitises the incoming signal with a high-speed ADC and then equalises and detects it in digital logic, instead of doing that processing in analog circuits.
Why did PAM4 push the industry towards DSP?
PAM4 has smaller eyes and needs more precise equalisation on lossy channels. Doing that with long digital filters and sequence detection is more practical than with analog taps at around 50 GBd.
Will analog SerDes disappear?
Unlikely. Short-reach and low-power links still favour lighter analog designs, and every DSP SerDes relies on high-performance analog front ends and clocking.
Who is Alphawave Semi?
Alphawave IP Group, trading as Alphawave Semi, develops high-speed connectivity IP, custom silicon and chiplets. Qualcomm completed its acquisition of the company in December 2025.
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