- VHDL is verbose, complicated and confusing
- Many different ways of saying the same thing
- Constructs that have similar purpose have very different syntax (case vs. select)
- Constructs that have similar syntax have very different semantics (variables vs signals)
- Hardware that is synthesized is not always obvious (when is a signal a flip-flop vs latch vs combinational)
- VHDL supports unsynthesizable constructs that are useful in writing high-level models, testbenches and other non-hardware or non-synthesizable artifacts that we need in hardware design.
- VHDL can be used throughout a large portion of the design process in different capacities, from specification to implementation to verification.
- VHDL has static typechecking—many errors can be caught before synthesis and/or simulation.
- VHDL has a rich collection of datatypes
- VHDL is a full-featured language with a good module system (libraries and packages).
- VHDL has a well-defined standard.
- VHDL vs Verilog
- Verilog is a "simpler" language: smaller language, simple circuits are easier to write
- VHDL has more features than Verilog
- richer set of data types and strong type checking
- VHDL offers more flexibility and expressivity for constructing large systems.
- The VHDL Standard is more standard than the Verilog Standard
- VHDL and Verilog have simulation-based semantics
- Simulation vendors generally conform to VHDL standard
- Some Verilog constructs don't simulate the same in different tools
- VHDL is used more than Verilog in Europe and Japan
- Verilog is used more than VHDL in North America
- South-East Asia, India, South America - More Democratic
- VHDL vs SystemC
- System C looks like C —familiar syntax
- C is often used in algorithmic descriptions of circuits, so why not try to use it for synthesizable code as well?
- If you think VHDL is hard to synthesize, try C....
- SystemC simulation is slower than advertised
- VHDL vs Other Hardware Description Languages
- Superlog: A proposed language that was based on Verilog and C. Basic core comes from Verilog. C-like extensions included to make language more expressive and powerful. Developed by the Co-Design company, but no longer under active development. Superlog has been superseded by SystemVerilog, see below.
- SystemVerilog: A language originally proposed by Co-Design and now standardized by Accellera, an organization aimed at standardizing EDA languages. SystemVerilog is inspired by Verilog, Superlog, and System-C. SystemVerilog is a superset of Verilog aimed to support both high-level design and verification.
- Esterelle: A language evolving from academia to commercial viability. Very clean semantics. Aimed at state machines, limited support for datapath operations.
Your comments will be moderated before it can appear here. Win prizes for being an engaged reader.