* Allows the designer to insert debug logic and view results directly in the RTL source code.
* Allows FPGA to run at normal design speed, but still allows debug access.
* Allows the designer to set triggers on signals and their values (data path), as well as trigger on RTL code branches such as CASE and IF statements.
* Allows the designer to view the captured data from the FPGA in almost any waveform display. Provides standard VCD output for results.
* Provides VHDL models for waveform data with all the type information and data included allowing the designer to view results in a waveform display complete with all the VHDL type information that they want to see.