Digital "Square root" Computation of a number


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module sqrt (clk,data,start,answer,done);
input clk,start;
input [7:0] data;

output [3:0] answer;
output done;


reg [3:0] answer;
reg busy;

reg [1:0] bit;

wire [3:0] trial;


assign trial = answer | (1 << bit);

always @ (posedge clk)
begin
if (busy)
begin
if (bit == 0) busy <= 0;
else
bit <= bit - 1;

if (trial*trial <= data)
answer <= trial;
end
else if (start)
begin
busy <= 1;
answer <= 0;

bit <= 3;
end
end

assign done
= ~busy;
endmodule

{ 3 Reactions ... read them below or write one }

Anonymous said on November 27, 2012 at 9:42 PM

So your solution is trial and error? This seems terribly inefficient, especially for hardware.

Guest Blogger said on November 28, 2012 at 6:09 AM

Can we see your solution,?

Islombek Mamatov said on January 15, 2013 at 1:48 AM

(Step1) Input N

(Step2) Set XL=1, and XH=N

(Step3) Set XM = (XL+XH) / 2 (Round if necessary)

(Step4) If XH-XL < 2 Then

STOP. Result is XM

(Step5) If XM * XM > N Then

set XH = XM

else

set XL = XM

(Step 6) Goto Step3

i have this algorithm, how i can impelent it in verilog? please can you help?

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