Verilog - Multiplication Gotcha, did you ever know?!

The Administrator
Written by
1
Did you know this basic gotcha of verilog :-) ?

You can use the "*" operator to multiply two numbers:
wire [9:0] a,b;
wire [19:0] result = a*b; // unsigned multiplication!

If you want Verilog to treat your operands as signed two's complement numbers, add the keyword signed to your wire or reg declaration:
wire signed [9:0] a,b;
wire signed [19:0] result = a*b; // signed multiplication!

Remember: unlike addition and subtraction, you need different circuitry if your multiplication operands are signed vs. unsigned. Same is true of the >>> (arithmetic right shift)
operator. To get signed operations all operands must be signed.

To make a signed constant: 10'sh37C
--
Create your RupeeMail Account & refer your friends to earn launch referral bonus on every new registration.
Try this... http://www.rupeemail.in/rupeemail/invite.do?in=MTUyNjUlIyVSajZ5dlBocDhrU3ozWVZ3bTBhZWQyQ2ZF

Post a Comment

1Comments

Your comments will be moderated before it can appear here. Win prizes for being an engaged reader.

  1. Will a signed number whose sign bit has been truncated be considered as signed? And what if that number's 2's complement is multiplied to it, what method will be used? Thank you for your time.

    ReplyDelete
Post a Comment

#buttons=(Ok, Go it!) #days=(20)

Our website uses cookies to enhance your experience. Learn more
Ok, Go it!