You can use the "*" operator to multiply two numbers:
wire [19:0] result = a*b; // unsigned multiplication!
If you want Verilog to treat your operands as signed two's complement numbers, add the keyword signed to your wire or reg declaration:
wire signed [19:0] result = a*b; // signed multiplication!
operator. To get signed operations all operands must be signed.
To make a signed constant: 10'sh37C
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