Showing posts with label Debugging. Show all posts
Showing posts with label Debugging. Show all posts

VSIDE - VSDSP Integrated Development Environment


VLSI Solution has announced VSIDE - the Integrated Development Environment for VSDSP Processor Family. VSIDE is an integrated development environment for VLSI Solution's 16/40-bit VSDSP digital signal processor family. It contains a complete set of development utilities, including an optimizing ANSI-C compiler, assembler, linker, profiler, etc. All programs are integrated into a simple-to-use, easy-to-learn package running on a PC / Windows XP or Vista platform.

VSIDE supports emulator-based debugging using real hardware. It also contains several example projects to help users get easily started. The beta version of the tool has been successfully used in the development of many audio products such as echo cancellation for Skype phone and pitch shifting of the audio source for a portable karaoke product. DSPeaker's (www.dspeaker.com) award winning Anti-Mode™ algorithm was debugged in a short time by using the powerful tools of VSIDE.

VSIDE currently supports VLSI Solution's audio codec chip VS1053 as well as VLSI's all-new digital signal processor circuit VS8053. Support for the low cost VS1000 audio system chip will be added by Q1/2011. VLSI Solution's current programming examples will gradually be ported to VSIDE.

Keeping with the spirit of VLSI Solution's openness policy, VSIDE can be downloaded for free at: http://www.vlsi.fi/en/support/software/vside.html

About VLSI Solution
VLSI Solution is an innovative new technology creator that designs and manufactures integrated circuits. Within its 19 years of existence VLSI has build an extensive in-house IP library and has the capability to pull through complicated mixed-signal IC projects, ranging from digital audio to RF applications.

For more information, see http://www.vlsi.fi/

Source Navigator for Verilog


Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many Verilog files. It parses Verilog code into a database that can be used to navigate files, trace connectivity, and find modules and signals in the design. It can even parse your files as you edit so you don't launch those long compile scripts only to end up with a syntax error after 5 minutes of compiling.

Source Navigator was developed by Cygnus Software as a commercial IDE (Integrated Development Environment) for software engineers and was later released under the GPL by Red Hat. Source Navigator supports many languages including C, C++, Tcl, Java, Fortran, and COBOL. There are so many similar products for software engineers, but almost nothing available for hardware engineers using languages such as Verilog. By adding a Verilog parser to Source Navigator hardware engineers can now enjoy the same high quality software.

Comit-TX Verilog Testbench Extractor


Comit-TX extracts a self-checking Verilog testbench of any module inside a design that has a system level testbench. Comit-TX, with the extracted testbench, enables the module's replacement to be verified in a stand-alone basis in an environment identical to its final working environment, without having to simulate the entire system.

nECO for Verdi and Debussy debug systems


nECO is an integrated graphical netlist modification tool for the Verdi and Debussy debug systems. The Novas debug systems accelerate users' understanding of complex designs to improve design, verification, and debug productivity. nECO adds the ability to isolate logic that needs to be changed in a flattened schematic, make the necessary changes, and write the modified design to a new netlist file.

Functionally debug in RTL source using Identify RTL Debugger


The Identify RTL Debugger lets FPGA designers and ASIC prototyping designers to functionally debug their hardware directly in their RTL source code. This allows functional verification with RTL designs 10,000 times faster than RTL simulators, and enables the use of in-system stimulus for applications like networking, audio and video, and HW/SW designs. Identify software allows designers to directly select signals and conditions in their RTL source code for debugging and the results are viewed directly in the RTL source code. The Identify tool can also save results in standard VCD format that can be used with most waveform viewers.

Key Features:
* Allows the designer to insert debug logic and view results directly in the RTL source code.
* Allows FPGA to run at normal design speed, but still allows debug access.
* Allows the designer to set triggers on signals and their values (data path), as well as trigger on RTL code branches such as CASE and IF statements.
* Allows the designer to view the captured data from the FPGA in almost any waveform display. Provides standard VCD output for results.
* Provides VHDL models for waveform data with all the type information and data included allowing the designer to view results in a waveform display complete with all the VHDL type information that they want to see.

Gatevision for Netlist debugging


GateVision  is a standalone graphical netlist analyzer that allows intuitive design navigation, schematic viewing, logic cone extraction, interactive logic cone viewing, and design documentation. GateVision's easy-to-read schematics and schematic fragments provide excellent debug support and accelerate the debug process.

Key Features:

   * On-the-fly schematic creation results in very high speed and capacity
   * Automatically extracts logic cones from user-defined reference points, and shows just the important portion of the circuit
   * Interactive logic cone navigation Allows compelling signal path tracing through the complete design hierarchy
   * Search-and-show capability allows easy location of specific objects shortens debug time
   * Design hierarchy browser provides easy navigation through the design hierarchy and gives compact hierarchy overview
   * Object cross-probing highlights selected objects in all design views (schematic, logic cone and HDL view) and shortens debug time
   * Context-sensitive menus and easy-to-use GUI
   * Verilog and EDIF netlist interface allows integration s into almost any design flow
   * Userware API allows addition of custom features

The Art of Debugging: Make it Fail


"Debugging" is the most valuable engineering skills, not taught in any formal setting, and often learned the hard way, by trial, error, experience, and long days and nights. These excerpted chapters, part1, part2, part3 from a book, Debugging: The 9 Indispensable Rules for Finding Even the Most Elusive Software and Hardware Problems, published by AMACOM Books is informative and a logical introduction to the skill and art of begging electronic circuits and systems.