Functionally debug in RTL source using Identify RTL Debugger

The Identify RTL Debugger lets FPGA designers and ASIC prototyping designers to functionally debug their hardware directly in their RTL source code. This allows functional verification with RTL designs 10,000 times faster than RTL simulators, and enables the use of in-system stimulus for applications like networking, audio and video, and HW/SW designs. Identify software allows designers to directly select signals and conditions in their RTL source code for debugging and the results are viewed directly in the RTL source code. The Identify tool can also save results in standard VCD format that can be used with most waveform viewers.

Key Features:
* Allows the designer to insert debug logic and view results directly in the RTL source code.
* Allows FPGA to run at normal design speed, but still allows debug access.
* Allows the designer to set triggers on signals and their values (data path), as well as trigger on RTL code branches such as CASE and IF statements.
* Allows the designer to view the captured data from the FPGA in almost any waveform display. Provides standard VCD output for results.
* Provides VHDL models for waveform data with all the type information and data included allowing the designer to view results in a waveform display complete with all the VHDL type information that they want to see.