Showing posts with label FPGA. Show all posts
Showing posts with label FPGA. Show all posts

Driving Flexibility into Automotive Electronics Design


With the dramatic increase in development costs for state-of-the-art process technologies, such as next-generation automotive electronic systems, specialization of traditional microcontrollers no longer makes business sense. This white paper discusses a process to develop an exact microcontroller for a specific application by implementing it into an Altera Cyclone IV FPGA for prototyping and volume production. Verification, software development, and field testing can be done immediately after design or even in parallel.

Protect Your FPGA Against Piracy: Cost-Effective Authentication Scheme Protects IP in SRAM-Based FPGA Designs


This application note describes FPGAs (field-programmable gate arrays) and how they can hold the key functions and the intellectual property (IP) of a system. It discusses ways to protect IP against piracy. SHA-1 challenge-and-response authentication is judged as the most secure methodology. This document presents a cost-effective authentication scheme that protects IP in SRAM-based FPGA designs. The DS28E01 and DS28CN01 1-Wire devices are featured.

How to Inexpensively Design an ASIC in 5 Weeks


If you have ever designed a standard cell ASIC from scratch, you probably still have the scars to show for it. Designing a standard cell ASIC is not for the weak-hearted. A new generation of ASIC, (dubbed the NEW ASIC), is gaining momentum as an alternative to both standard cell ASIC and FPGA design which is explained in this paper. This new generation of ASIC combines the fast turnaround, low up-front development costs and simple design flow benefits that are normally associated with FPGAs, with the low unit power consumption and cost approaching that of a standard cell ASIC.

SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits


SPARK is a C-to-VHDL high-level synthesis framework that employs a set of innovative compiler, parallelizing compiler, and synthesis transformations to improve the quality of high-level synthesis results. SPARK takes behavioral ANSI-C code as input, schedules it using speculative code motions and loop transformations, runs an interconnect-minimizing resource binding pass and generates a finite state machine for the scheduled design graph. Finally, a backend code generation pass outputs synthesizable register-transfer level (RTL) VHDL. This VHDL can then by synthesized using logic synthesis tools into an ASIC or can be mapped onto a FPGA.

Diagnosing clock domain crossing errors in FPGAs


Clock domain crossing (CDC) errors in FPGAs are elusive, and locating them often requires good detective work and smart design as well as an understanding of metastability and other physical behaviors. This white paper discusses the nature of CDC errors and presents a powerful solution that aids in their detection and removal.Note: By clicking on the above link, this paper will be emailed to your TechOnline log-in address by Mentor Graphics.

OpenFPGA


OpenFPGA is an emerging effort to foster and accelerate the adoption and incorporation of reconfigurable computing based computing solutions in high-performance computing and enterprise application environments. OpenFPGA will foster shared and open efforts to address challenges of portability, interoperability and intra-application communication for FPGA and reconfigurable applications in high-performance and enterprise computing environments.

Teaching Embedded Systems using ARM and FPGAs


Prof. Saeid Nooshabadi of the University of New South Wales in Sydney, Australia, has an excellent website describing his course and the accompanying laboratory-based exercises. Emphasis is placed on interfacing the ARM processor to other programmable hardware devices. Students use GNU tools operating under Linux to compile and simulate C, C++ and assembly-language programs. FPGA development is performed using Xilinx ISE WebPack and ModelSim-XE operating under Microsoft Windows. Click for additional information!

ASIC equivalent gates for Virtex


4-input LUT 6
4-input ROM 32
3-input LUT na
16x1 RAM 64
32x1 RAM 128
16 Shift Reg LUT 64
CLB flop 8
CLB latch 5
IOB flop 8
IOB latch 5
IOB Sync latch na
TBUF 3
Block RAM 16,384
BSCAN 48
Clk DLL 7,000
F5 MUX 3
F6 MUX 3
MUXCY 3
XORCY 3

If you do some quick math, one can calculate the typical ASIC gates for a
Virtex 1000, which has a 64x96 CLB array:
( 64*96 CLB )* ( 2 Slices/CLB )* ( 20 Gates/Slice ) = 245,760 Gates.

FPGA & ASIC based design


The main diferrence between ASIC and FPGA based design is in the Back-end.
In FPGAs there is not much activities in back end.

FPGA flow:
SPECIFICATION -> RTL DESIGN -> FUNCTIONAL SIMULATION -> SYNTHESIS -> TRANSLATION -> MAPPING -> PLACE & ROUTE -> BITGEN GENERATION -> DOWNLOAD TO THE CHIP.

ASIC flow:
SPECIFICATION -> RTL DESIGN -> FUNCTIONAL SIMULATION -> SYNTHESIS -> EXTRACT RC VALUES -> DRC, LVS,etc., -> LIBRARY VENDOR SPECIFIC FILE FORMAT

Coarse and Fine grained architectures


Coarse-grained architectures consist of fairly large logic blocks, often containing two or more look-up tables and two or more flip-flops. In a majority of these architectures, a four-input look-up table (think of it as a 16x1 ROM) implements the actual logic. The larger logic blocks usually corresponds to improved performance.

Fine-grained circuits, consist of the basic cell being simple (OR, AND,and NOT).