Showing posts with label VN-Cover. Show all posts
Showing posts with label VN-Cover. Show all posts

EDA Tools - VN-Cover Emulator Coverage Analysis for HW Emulation


VN-Cover Emulator by TransEDA enables engineers to obtain coverage on their SoCs in a hardware-accelerated environment and reach a level of confidence similar to that achieved using VN-Cover with software simulators. Using VN-Cover Emulator speeds up the overall verification task by providing better visibility on what has been covered, what is left, and when to stop verification.

Key Features:

* Coverage for statement, branch, toggle and FSM state and arc
* Verilog, VHDL and mixed-language support
* Detailed code coverage reports and graphical display
* Automatic FSM extraction and analysis
* Support for Cadence Palladium and Cobalt, EVE Zebu, Mentor Graphics Celaro and Vstation, and Verisity Xtreme

EDA Tools - VN-Cover Coverage Analysis


VN-Cover by TransEDA is a code and FSM coverage tool that identifies any unverified parts of a simulated HDL design. VN-Cover includes a comprehensive set of metrics, which include line, statement, branch, condition, path, toggle, triggering, signal trace and FSM state, arc and path. In addition, the tool offers advanced features such as Deglitch and Coverability Analysis option, aimed at increasing measured coverage accuracy.

VN-Cover seamlessly works with all leading simulators to measure coverage on VHDL, Verilog, SystemVerilog and mixed-language designs. It is a vendor-neutral coverage tool that works across simulators, languages and platforms, and can be also utilized with hardware-accelerated verification environments.
Key Features:

* Verilog, VHDL and mixed-language support
* Detailed code coverage reports and graphical display
* Automatic FSM extraction and analysis
* Advanced and unique glitch filtering capability
* Post-simulation coverability analysis option and results filtering
* Test-suite optimization facility
* Multi-platform, multi-simulator availability