Showing posts with label papers. Show all posts
Showing posts with label papers. Show all posts

Improving IC Design Productivity with an Integrated Hardware Configuration Management System


Like software teams, hardware design teams need configuration management systems. However, Software Configuration Management (SCM) systems do not meet all the demands of hardware design teams. This paper explains the drawbacks of traditional data sharing and collaboration techniques and how a Hardware Configuration Management (HCM) system integrated into the design flow can enhance collaboration, improve productivity and dramatically reduce the need for re-spins.

10 Reasons to Customize a Processor Core


There are plenty of really good, proven processor cores on the market today. But if you have more than simple control tasks, perhaps you've considered using a processor that you can customize. This paper discusses 10 good reasons why you should consider customizing your core in your next SoC design.

PCI Express-based MicroTCA Design Options


PCI Express-based MicroTCA platforms are generating more and more interest. This paper describes how small and cost-effective MicroTCA platforms can be built utilizing PCI Express. Furthermore, architecture options for multiprocessor implementations are described, including both standalone systems and clusters.

Improving I/O Virtualization Performance with PCI Express


Virtualization technology has been used in high-end servers for quite some time. The evolution of virtualization has brought with it the desire to reduce the software (S/W) overhead portion of virtualization, particularly for I/O devices. This paper will begin with an introduction to the general concepts of virtualization and I/O virtualization. It will then discuss how I/O virtualization is addressed within the PCI Express specification and the changes required to add I/O virtualization support to an existing PCI Express interface. Additional PCI Express topics covered include: Single-Root I/O Virtualization (SR-IOV), Function Level Reset (FLR), Alternative Routing ID (ARI) and Address Translation Services (ATS).

Memory Management Technique Speeds Apps By 20%


A paper (PDF) to be presented later this month at the IEEE International Parallel and Distributed Processing Symposium in Atlanta describes a new approach to memory management that allows software applications to run up to 20% faster on multicore processors. Yan Solihin, associate professor of electrical and computer engineering at NCSU and co-author of the paper, says that using the technique is just a matter of linking to a library in a program that makes heavy use of memory allocation. The technique could be especially valuable for programs that are difficult to parallelize, such as word processors and Web browsers. {Via Slashdot}

Logical and Physical Design Reuse


Electronics designs have become extremely complex and intricate, creating a need for software tools that support automation, maintain accuracy, and meet short design cycles. Re-using previously designed circuitry has long been an option for meeting these needs, but has never been easy to implement. Software providers have made attempts at providing this capability, but their solutions haven't always caught on. With new, more efficient options at hand, will customers see the value? Will they give it a try? This paperintroduces a methodology that can handle today's data-filled design content and still produce proper, reusable designs.

Electronic System Level (ESL) Design using VaST tool


ESL design and verification is an emerging electronic design methodology that focuses on the higher abstraction level. The basic essence is to model the behavior of the entire system using a high-level language such as C, C++, SystemC or SystemC TLM-2.0. ESL is evolving into a set of methodologies that enable embedded system design, hardware verification, debugging through to the hardware and software implementation of custom SoC, and Architecture and Performance analysis as well. This paper discusses Electronic System Level (ESL) design and the methodologies and the tools associated with it.

FPGA Design Methods for Fast Turn Around


Today's FPGAs are doubling in capacity every 2 years and have already surpassed the 5 million equivalent ASIC gate mark. With designs of this magnitude, the need for fast flows has never been greater. At the same time, designers are seeking rapid feedback on their ASIC or FPGA designs by implementing quick prototypes or initial designs on FPGA-based boards. These prototypes or designs allow designers to start development, verification and debug of the design—in the context of system software and hardware—and also to fine tune algorithms in the design architecture. Quick and intuitive debug iterations to incorporate fixes are of great value. The ability to perform design updates that don't completely uproot all parts of the design that have already been verified is also a bonus! Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.

Reduce Power, Area and Routing Congestion


This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare Interconnect Fabric for the ARM AMBA 3 AXI while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to meet the stringent timing requirements. Detailed technical analysis is provided for the selected architecture, pipelining mode, arbitration scheme and the slave visibility feature employed to reach timing closure for the links with demanding performance requirements. Final results are presented based on the hybrid architecture of the DesignWare Interconnect Fabric used to optimize the infrastructure resulting in a reduction in area, power and routing congestion.

Major Benefits of IEEE-1149.7(Compact JTAG)


This paper provides a summary of the features and benefits from the new IEEE-1149.7 specification commonly referred to as compact JTAG (cJTAG) which builds on existing IEEE-1149.1 boundary-scan architecture.

Processor Affinity or Bound Multiprocessing?


Migrating systems designed for single core processors to multicore environments is still a challenge. Bound multiprocessing (BMP) can help with these migrations. It improves SMP processor affinity. It allows developers to bind all threads (including dynamically created threads) in a process or even a subsystem to a specific processor without code changes.

Getting Started with Android Development for Embedded Systems


Android is an open source platform built by Google that includes an operating system, middleware, and applications for the development of devices employing wireless communications. This paper takes a look at the design of Android, how it works, and how it may be deployed to accelerate the development of a connected device. Along with basic guidelines to getting started with Android, the Android SDK, its available tools and resources are reviewed and some consideration is given to applications for Android beyond conventional mobile handsets such as medical devices, consumer electronics and military/aerospace systems.

Digital Signal Processing: A Practical Guide


This book is intended for those who work in or provide components for industries that use digital signal processing (DSP). There is a wide variety of industries that utilize this technology. While the engineers who implement applications using DSP must be very familiar with the technology, there are many others who can benefit from a basic knowledge of its' fundamental principles, which is the goal of this book—to provide a basic tutorial on DSP. Checkout these Part1, Part2, Part3 which are actually chapter extracts from the original book.

Hot papers at 2009 VLSI Technology Symposium


Hot papers from this year's VLSI Technology Symposium include three nonvolatile memory advancements: Toshiba' BiCS Flash, Samsung's vertical-stacked transistor structures and Hitachi's PCRAM. Two papers on advanced logic processes include: Intel's" High-k/Metal Gate Stacks" and IBM's "32nm SOI CMOS with Highk/ Metal Gate."

Most Significant Papers on IC Test


Many important papers have been presented at the annual International Test Conference (ITC) over the past 35 years. The best of these are on-line at ITC Papers.

VLSI Conference 2008 - Hyderabad, India


Did you know that you can access the complete conference CD including sessions and papers.

Please visit
http://conferences.homeip.net

Register for free and have fun.