Electronic System Level (ESL) Design using VaST tool

ESL design and verification is an emerging electronic design methodology that focuses on the higher abstraction level. The basic essence is to model the behavior of the entire system using a high-level language such as C, C++, SystemC or SystemC TLM-2.0. ESL is evolving into a set of methodologies that enable embedded system design, hardware verification, debugging through to the hardware and software implementation of custom SoC, and Architecture and Performance analysis as well. This paper discusses Electronic System Level (ESL) design and the methodologies and the tools associated with it.

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