Phase-locked loops (PLLs) Demystified
Over the past decade, Phase-Locked Loops (PLLs) have become an integral part of the modern ASIC design. PLLs provide th…
Over the past decade, Phase-Locked Loops (PLLs) have become an integral part of the modern ASIC design. PLLs provide th…
Clock domain crossing (CDC) errors in FPGAs are elusive, and locating them often requires good detective work and smart…
Most failures are not single-point; generally a single event does not entirely account for the failure. Often multiple …
This book is intended for those who work in or provide components for industries that use digital signal processing (DS…
"Debugging" is the most valuable engineering skills, not taught in any formal setting, and often learned the …
Many embedded system-on-a-chip (SoC) designs make use of multiple processors, but do so in an application-specific or &…
Hardware design data and design flows present unique requirements that are not met by software configuration management…
According to Mitch Weaver, corporate vice president for front-end verification at Cadence, the e verification language…
Broadcom recently announced a single-chip HSUPA baseband processor that integrates key 3G mobile technologies and will…
How many times in the course of a project have you heard of the term Formal Verification? This relatively short on arti…
In this article Richard Goering talks about a software bug in Toyota Prius 2005 and after 5 years even after a through…
Many of you already know that verification efforts are as or more important as the design efforts themselves. They cann…
Featured Tutorial: Step-By-Step Guide to Advanced Verification Tutorial!, DVcon Exhibits and Product Demos.., DVCon Pap…
This Mentor's Verification Academy module directly addresses CDC issues by introducing a set of steps for advancing…
Mode details about Free Simulators are here -> https://blog.digitalelectronics.co.in/2023/03/free-hdl-simulators.ht…
Mentor Graphics provides the Methodology kit examples in open source form under the Apache-2.0 license. These kits are…
This matrix illustrates (SupportNet access needed) the version compatibility between Questa SV/AFV and different versio…
DVClub is a very interesting organization. With chapters in Austin, Bangalore, Boston, Dallas, Research Triangle Park,…
Case Study:SystemVerilog VMM vs. BSV for an Ethernet MAC test bench. High-level verification languages and environment…
Today, cars can have as many as 70 electronic control units, or ECUs, based on microcontrollers (sometimes generically …
It is not completely correct to say that we have to avoid latches in our designs. In one of our recent projects we went…
By now you would have digested enough info about iPad from all the overflowing blogs and sites that are covering Apple…
A CPU has a memory unit with 32-bit instructions and a register file with 32 registers. The instruction set consists of…
Draw the circuit diagram for barrel-shifter that can shift 3 bits in either direction. The shifter should take 3 bits a…
In this article we will see how to create a simple Tcl script that tests for certain values on a signal and then adds b…