Delivering synthesizable verification IP for testbences

Case Study:SystemVerilog VMM vs. BSV for an Ethernet MAC test bench.
High-level verification languages and environments such as e/Specman, Vera and now SystemVerilog, as used in VMM or OVM, may be the state-of-the-art for writing test bench IP, but they are not synthesizable for developing models, transactors and test benches to run in FPGAs for emulation and prototyping. So engineers wishing to move verification assets onto FPGAs have been designing with RTL, the same old slow, resource-intensive and error-prone way.

But now, with the introduction of modern high-level languages for synthesizable verification IP, engineers can design test benches, models and transactors at a high level of abstraction and with extreme reuse, but they can also synthesize them onto FPGAs – and they can do this as easily as they do today in simulation-only verification environments. Imagine running your test benches, models and transactors at tens of MHz.

This White Paper outlines important attributes of, and the applications for, modern high-level synthesizable verification environments. Using the example of a test bench for an Ethernet MAC, the paper compares the implementation of a synthesizable test bench done with Bluespec’s BSV with a non-synthesizable reference test bench done with SystemVerilog VMM – and it demonstrates that a synthesizable test bench can be implemented with fewer lines of code than using state-of-the-art SystemVerilog.

Outline:
Introduction
Features of an Ideal High-Level Synthesizable Verification Environment
Applications for High‐Level Synthesizable Verification
Case Study: SystemVerilog VMM vs. BSV for an Ethernet MAC test bench
Conclusion

Download a free copy of this whitepaper!