Are latches really bad for a design?

It is not completely correct to say that we have to avoid latches in our designs. In one of our recent projects we went a good extent debating only the disadvantges of using latches and then we had to can all the latches because many were not convinced. There are cases where you can safely use latches, just that you have to be little careful and the designer needs to be really sure of the impending functionality. In this post lets look at all possible cases where latches are preferred and where they are not. If you think if any of the statements are wrong, lets have a healthy debate.

The bad guys (Please add more):
1. One of the main reasons that latches are not used in designs is due to combinational loop back and subsequent oscillation which creates super problems in simulation, and also simulation Vs synthesis mismatches.
2. Due to controllability issues in latches unlike FF's, they can significantly harm STA/DFT and thereby reduce coverage in both cases.
3. The major factor for the above uncontrollability are Glitches in the enable pin of the latches that can cause unrecoverable failure
4. Last but not the least.. :-) the biggest culprit of all... inferred latches after synthesis due to bad coding styles.

1. Latches consume less power and area compared to FF's
2. If the design is not power aware, FF's are prefered and almost all the latches could be replaced by FF's without affaecting functionality.
3. Remember that the decode of a latched address can begin before the latch is actually closed..:-)

Corrective Measures:
1. A glitch-free enable helps if latches are unavoidable.
2. If you are synthesizing the code that generates the enable, please consider the direct instantiation of the logic using gates that drives the enable to the latch. Now you can be double sure!
3. A good input hold time ensures that the data is held long enough before you close the latch. If your latch enable is derived from a clock, the latch will lag the clock, requiring the latch's D inputs to be held valid after the clock edge.

NOTE: The latch has a disadvantage of being "transparent" till the clock makes the latch the value of the input. The FF samples the input on the risinf or falling edge of the clock.

If you are not careful.... when developing synchronous digital designs, latches can generate asynchronous circuits that become unstable.

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  1. This a good information.and good point.let us think about the matter deeply

  2. combinational loopback - how about showing a diagram explaining how it occurs in latches? that is of course, if you want your article to be THE point of reference for good v.s. bad about latches on the internet.


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