Comp Arch - Pipelining


Pipelining is an implementation technique where multiple instructions are overlapped in execution. It not decrease the time for each instruction execution, instead it increases instruction throughput.

Throughput of the instruction pipeline is determined by how often an instruction exits the pipeline.

Logic Hazards


Some basics before we head further...

Steady State Behaviour:
Value of o/p after the i/p's have been steady for some time.

Transient Behaviour:
Value if o/p while the i/p is changing.

Glitch:
Short pulse produced in the o/p during the transient phase.

Static Hazards:
One glitch when you are expecting a steady o/p.
  • Static - 1: Encounter of a 'Zero' glitch when expecting steady 'One'.
  • Static - 0: Encounter of a 'One' glitch when expecting steady 'Zero'.
Ways to eliminate static hazards:
  • Identify possibilities in a K-MAP.
  • Write Minimal form for the final expression.
  • Observing the Two adjacent 1's in a K-MAP that are not in the same term is a possible cause.
  • Use the 2 adjacent 1's, make a redundant logic and add to the final expression.
Dynamic Hazards:
Multiple glitches when you are expecting a steady o/p.
These persist when multiple paths with different delays are existant between a changing input and an output.

Ways to eliminate Dynamic Hazards:
  • Proper design of AND-OR (or) OR-AND circuit.
  • Two level design of above, if a variable and its complement are never inputs to the same first level gate.

Further, check http://www.cs.ualberta.ca/~amaral/courses/329/webslides/Topic7-TimingHazards/sld001.htm