FIFO Depth Calculator

An interactive tool to size First-In-First-Out (FIFO) buffers for VLSI, FPGA and ASIC designs — plus the theory, the depth formula, and worked examples behind every result.

On this page

• Interactive FIFO depth calculator
• What FIFO depth means and why it matters
• The FIFO depth formula (and how to derive it)
• Worked examples
• How to use the calculator
• Tips for accurate results
• Frequently asked questions

Introduction to the FIFO Depth Calculator

First-In-First-Out (FIFO) buffers are essential in VLSI design for moving data between different clock domains or processing stages in systems such as SoCs, FPGAs and ASICs. Getting the FIFO depth right is a balancing act: too shallow and you drop data on overflow; too deep and you waste silicon area and power.

This FIFO Depth Calculator is an interactive tool that helps you analyze FIFO behaviour under different data-arrival patterns. By entering clock frequencies, data rates and simulation cycles, you can evaluate queue depth, throughput and critical edge cases such as overflow (data lost when the FIFO is full) and underflow (a read attempted from an empty FIFO). It supports both synchronous (single-clock) and asynchronous (dual-clock) FIFOs, so it works for everything from streaming pipelines to clock-domain-crossing (CDC) interfaces.

Key features:

• Constant-rate analysis — simulate steady-state flow with custom input/output clock frequencies and data rates, ideal for streaming applications.
• Bursty arrivals — model sporadic bursts common on high-speed interfaces such as PCIe, USB and Ethernet.
• Asynchronous FIFO support — analyze dual-clock FIFOs and see the effect of a faster or slower write domain.
• Detailed results — queue depth over time in a table and chart, plus maximum, minimum and average depth, throughput, and overflow/underflow counts.

Interactive FIFO Depth Calculator

FIFO Depth (entries) Initial Entries Input Clock Freq (MHz) Input Data Rate (cycles/entry) Output Clock Freq (MHz) Output Data Rate (cycles/entry) Simulation Cycles Asynchronous FIFO (dual clock)

In synchronous mode the reader is driven by the single (input) clock, so the output-clock field is used only when Asynchronous FIFO is ticked. “Min Depth Required” is computed from an unbounded run (the true peak backlog); overflow/underflow reflect your configured FIFO depth.

What FIFO depth means and why it matters

FIFO depth is the number of entries a FIFO can store. You need a FIFO whenever the side writing data and the side reading it don't move at the same instantaneous rate — either because they run on different clocks, or because data arrives in bursts while it drains steadily.

The insight that drives every depth calculation is simple: during a burst, if data is written faster than it can be read, the surplus has to be stored somewhere. That surplus — the peak backlog — is the minimum depth your FIFO must provide to avoid dropping data.

Important: a finite FIFO only solves a finite mismatch. If the write rate stays higher than the read rate forever (a sustained stream, not a burst), no depth is large enough — the FIFO will eventually overflow. Depth sizing therefore applies to bursts of known length, where the read side has idle time between bursts to catch up.

The FIFO depth formula

Consider a burst of B data items. The FIFO must hold whatever cannot be read out while the burst is still being written:

FIFO Depth = (items written during the burst) − (items read during the burst)

To turn that into numbers, work out how long the burst takes to write, then how many items are read during that same window:

1. Time to write the burst = B × d_in ÷ f_in
   (where f_in is the write clock and d_in is the write data rate in clocks per entry — 1 means one entry every clock, 2 means one entry every two clocks, etc.)
2. Items read in that time = (time to write) × f_out ÷ d_out
3. Depth = B − (items read)

Combining the steps gives a single compact formula:

Depth = B × [ 1 − (d_in × f_out) ÷ (f_in × d_out) ]

For the common case of one entry per clock on both sides (d_in = d_out = 1), this reduces to the classic form every VLSI interview asks about:

Depth = B × ( 1 − f_out ÷ f_in )

Always round the result up to the nearest whole entry (and, if your design uses binary/Gray-code pointers, up to the next power of two).

Worked examples

Example 1 — Faster write clock (the classic case)

Write clock f_in = 80 MHz, read clock f_out = 50 MHz, burst B = 120 items, one entry per clock on each side.

• Time to write 120 items = 120 × (1 ÷ 80 MHz) = 1500 ns
• Items read in 1500 ns at 50 MHz = 1500 ns ÷ 20 ns = 75
• Depth = 120 − 75 = 45 entries

Check with the compact formula: 120 × (1 − 50/80) = 120 × 0.375 = 45. ✔

Example 2 — Idle cycles on the read side

Both clocks at 100 MHz, but the reader can only accept one entry every two clocks (d_out = 2), while the writer streams one per clock (d_in = 1). Burst B = 120.

• Time to write = 120 × (1 ÷ 100 MHz) = 1200 ns
• Items read = 1200 ns × (100 MHz ÷ 2) = 60
• Depth = 120 − 60 = 60 entries

Notice that equal clock frequencies still require a deep FIFO when the data rates differ — a point that trips up a lot of designers.

Example 3 — Modest CDC mismatch

f_in = 100 MHz, f_out = 80 MHz, burst B = 100, one entry per clock.

• Depth = 100 × (1 − 80/100) = 20 entries

Scenario	Write	Read	Burst	Required depth
Faster write clock	80 MHz, 1/entry	50 MHz, 1/entry	120	45
Read-side idle cycles	100 MHz, 1/entry	100 MHz, 2/entry	120	60
Modest CDC mismatch	100 MHz, 1/entry	80 MHz, 1/entry	100	20
Read ≥ write rate	50 MHz	≥ 50 MHz	any	0 (no buffering needed)

The calculator above automates exactly this arithmetic — and adds a cycle-by-cycle simulation so you can see when the peak occurs, not just its value. For a deeper walkthrough of nine variations (including same-frequency and read-faster cases), see the companion post on FIFO depth calculation.

Reproduce Example 1 in the tool: open the Constant Rate tab, tick Asynchronous FIFO, set input clock = 80 MHz, output clock = 50 MHz, both data rates = 1, and set Simulation Cycles = 120 (the burst length — the writer fills 120 entries, then the reader keeps draining). The reported Min Depth Required is 45, matching the formula. The Bursty Arrivals tab instead models each burst as an instantaneous arrival (the worst case for packet FIFOs), so its peak is closer to the full burst size — use whichever matches how data actually reaches your buffer.

How to use the FIFO Depth Calculator

The calculator offers two modes: Constant Rate for steady flows and Bursty Arrivals for intermittent bursts. Depth sizing (above) maps most directly onto the Bursty Arrivals mode; use Constant Rate to study sustained throughput, overflow onset and underflow.

Constant Rate mode

Simulates continuous input and output — useful for video/audio pipelines and any steady stream.

1. FIFO Depth (entries) — the buffer size in your design, e.g. 128.
2. Initial Entries — entries already in the FIFO at t=0 (e.g. 0 for empty).
3. Input Clock Freq (MHz) — the write clock, e.g. 100.
4. Input Data Rate (cycles/entry) — write clocks per entry; 1 = one entry per cycle, 2 = one entry every two cycles.
5. Output Clock Freq (MHz) — the read clock (e.g. 80 for async, or equal to input for sync).
6. Output Data Rate (cycles/entry) — read clocks per entry.
7. Simulation Cycles — how long to run, e.g. 1000.
8. Asynchronous FIFO — tick for a dual-clock FIFO; leave unticked for a single-clock (synchronous) FIFO.
9. Click Calculate.

Example: FIFO depth 128, initial 0, input 100 MHz at 1 cycle/entry, output 80 MHz at 1 cycle/entry, 1000 cycles, Asynchronous ticked. Because the write side is faster, you'll watch the queue climb and eventually report overflow — a vivid illustration of why a sustained rate mismatch can't be fixed by depth alone.

Bursty Arrivals mode

Models packet-style traffic seen on Ethernet, USB and DDR controllers.

1. FIFO Depth (entries) and Initial Entries as above.
2. Burst Sizes (comma-separated) — entries per burst, e.g. 50,30,20.
3. Burst Cycles (comma-separated) — the cycle at which each burst arrives, e.g. 100,200,300. The two lists must be the same length.
4. Output Clock Freq and Output Data Rate — the drain rate.
5. Simulation Cycles, then Calculate.

Example: depth 128, initial 0, burst sizes 50,30,20 at cycles 100,200,300, output 100 MHz at 1 cycle/entry, 1000 cycles. You'll see the queue spike at each arrival and drain between bursts — the maximum depth reported is the minimum FIFO size that keeps this traffic loss-free.

Reading the results

• Table — per cycle: current queue depth and status (Normal, Overflow or Underflow).
• Chart — queue depth over time, so you can spot growth, depletion or bursts at a glance.
• Statistics — maximum, minimum and average depth; overflow count (entries lost when full); underflow count (reads from empty); and throughput (entries processed per microsecond).

Tips for accurate results

• Size to the maximum depth. The peak in the chart, rounded up (to a power of two for pointer-based FIFOs), is your minimum safe depth.
• Validate your inputs. All values must be positive, initial entries can't exceed the FIFO depth, and the burst-size and burst-cycle lists must match in length.
• Use asynchronous mode for real CDC. When write and read clocks differ, add margin for synchronizer latency (typically two flip-flop stages) on top of the computed depth.
• Watch throughput, not just depth. Sustained throughput is capped by the slower side; the calculator's throughput figure tells you whether your design keeps up.
• Distinguish burst from sustained. If overflow keeps rising in Constant-Rate mode with a faster writer, the fix is rate control or a faster reader — not a bigger FIFO.

▶ Try the FIFO Depth Calculator

Related reading: FIFO Depth Calculation — theory and nine worked cases.

Frequently asked questions

How do you calculate FIFO depth?

Find the peak backlog during a burst: Depth = B × (1 − f_out/f_in) for one entry per clock, or Depth = B × [1 − (d_in·f_out)/(f_in·d_out)] when data rates differ, where B is the burst size, f is clock frequency and d is clocks per entry. Round up to a whole number.

What is the difference between synchronous and asynchronous FIFO depth?

The depth arithmetic is the same, but an asynchronous (dual-clock) FIFO crosses clock domains, so you add margin for pointer-synchronizer latency (usually two flip-flop stages) and use Gray-code pointers to avoid metastability. A synchronous FIFO shares one clock and needs no such margin.

Why does my FIFO overflow even though the average read rate equals the write rate?

Averages hide bursts. If data arrives in a burst faster than it can be read, the FIFO must buffer the surplus until the reader catches up during the gap. Size the FIFO to the peak backlog, not the average.

Does a faster read clock mean I need zero depth?

If the read rate is greater than or equal to the write rate for the entire burst, the reader never falls behind and the theoretical depth is zero. In practice a small FIFO (a few entries) is still used to absorb jitter and synchronizer latency.

Should FIFO depth be a power of two?

For FIFOs addressed by binary or Gray-code pointers, yes — rounding up to the next power of two keeps pointer wrap-around and full/empty detection simple. Round up from the computed minimum depth.