Analog Security in Multi-Die Systems and Edge Computing: Challenges, Solutions, and Future Trends

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The shift toward multi-die assemblies and the growing importance of sensor-driven analog data at the edge are spotlighting a critical yet underexplored issue: security in analog circuits. 

As the semiconductor industry evolves from traditional system-on-chip (SoC) designs to heterogeneous, multi-dimensional systems-in-package (SiPs) encompassing 2.5D, 3D, and 3.5D architectures new opportunities and challenges arise for analog integration. While these advancements loosen the constraints of on-chip real estate and enable greater flexibility in analog design, they also expose analog circuits to novel security vulnerabilities that have historically been overshadowed by digital security concerns. 

This article delves deeper into the technical, market, and security implications of analog circuits in modern chip design, while exploring emerging solutions and future directions.

The Evolving Role of Analog in Multi-Die Systems

Historically, security in SoC designs has been a predominantly digital concern. 

Digital circuits, particularly in data centers and high-end edge computing, benefit from well-established security protocols, such as encryption, secure boot, and hardware security modules (HSMs). 

Analog circuits, by contrast, have been constrained by their inability to scale with Moore’s Law, leading to their progressive marginalization in favor of digital-heavy mixed-signal intellectual property (IP). The limited on-chip area in planar SoCs forced analog components to shrink or be replaced, as analog designs don’t benefit from the same scaling advantages as digital transistors. 

However, the advent of multi-die assemblies is reshaping this dynamic.

In SiPs, analog dies can be fabricated at process nodes optimized for their performance rather than being forced to conform to the cutting-edge nodes used for digital logic. For instance, analog components like power management units, radio frequency (RF) transceivers, or sensor interfaces can be developed on mature nodes (e.g., 28nm or 40nm) where cost and reliability are favorable, then integrated into a package alongside advanced digital chiplets on 5nm or 3nm nodes. 

This flexibility not only reduces development costs but also enhances the potential for reusing silicon-proven analog IP across multiple designs, improving time-to-market and reliability.

Moreover, the heterogeneous and globally asynchronous nature of SiPs allows analog circuits to operate with greater independence. 

Unlike in monolithic SoCs, where analog signals are often disrupted by the noise from densely packed digital transistors, SiPs offer more physical space to isolate analog components, reducing signal interference and improving performance. This extra area can also accommodate larger analog dies, enabling more complex analog functionality, such as high-precision sensor interfaces or advanced analog-to-digital converters (ADCs).

However, these advantages come with a trade-off: increased exposure to security risks. 

In traditional SoCs, the dense integration of billions of transistors created a form of “security-by-density,” where subsystems like security processors were difficult to isolate or target. 

Multi-die assemblies, by contrast, compartmentalize functionality into distinct chiplets, making subsystem-to-subsystem communications more accessible. 

For example, a security processor chiplet communicating with a performance chiplet over a multi-chip package could be intercepted or tampered with, enabling attacks that were nearly impossible in monolithic designs. This necessitates point-to-point security mechanisms, such as encryption and authentication, for chiplet-to-chiplet interfaces, as neither side of the link can be inherently trusted.

Security Challenges in Analog Circuits

The security challenges in analog circuits are multifaceted, spanning physical, electrical, and systemic vulnerabilities. 

Unlike digital circuits, which operate in discrete binary states, analog circuits process continuous signals, making them susceptible to subtle manipulations that can go undetected. 

Below are key areas of concern:

1. Physical Layer Vulnerabilities

The physical interfaces used to move and convert analog data such as SerDes (serializer/deserializer) PHYs, ADCs, or RF transceivers are prime targets for attacks. 

For instance, thermal fuzzing (heating a chip to alter its behavior), electromagnetic fault injection, or laser-based attacks can distort analog signals, leading to incorrect data processing or system malfunctions. 

In safety-critical applications like automotive or aerospace, such distortions could have catastrophic consequences, such as misinterpreting sensor data for autonomous driving or navigation.

2. Side-Channel Attacks

Analog circuits are particularly vulnerable to side-channel attacks, where attackers exploit physical characteristics like power consumption, electromagnetic emissions, or timing variations to extract cryptographic keys or other sensitive information. 

In multi-die systems, the exposed chiplet interfaces amplify this risk, as attackers can probe inter-chiplet communications more easily than intra-SoC signals.

3. Sensor Degradation and Fault Injection

Sensors, which are inherently analog, are critical to edge applications, particularly in AI-driven systems for automotive, industrial, and IoT use cases. 

However, analog sensors degrade over time due to factors like noise, hot carrier effects, or bias changes, which can reduce their precision and make them more susceptible to fault injection attacks. 

For example, an attacker could inject a fault to skip authentication steps in a secure boot process, allowing unauthorized code to run. 

To counter this, sensors often require recalibration or redundancy, but these measures increase cost and power consumption, posing trade-offs in performance-constrained environments.

4. Counterfeit Chiplets in Open Marketplaces

As the chiplet ecosystem evolves, third-party chiplets are expected to proliferate, creating an open marketplace. 

While this fosters innovation and reduces costs, it also introduces risks of counterfeit or malicious chiplets. A bad actor could design a chiplet that appears functional but contains backdoors or vulnerabilities, compromising the entire system. 

Building security against side-channel attacks and ensuring chiplet authenticity are critical for a viable chiplet era.

Analog Security at the Edge

The proliferation of AI and machine learning (ML) at the edge is amplifying the importance of analog security. 

Edge devices, such as autonomous vehicles, smart sensors, and IoT nodes, rely heavily on analog data from sensors to interact with the physical world. This data is increasingly valuable, not only for real-time decision-making but also for training ML models. Securing this data requires a paradigm shift in how analog circuits are designed and protected.

One approach is to make sensors “smarter” by integrating cryptographic capabilities. 

For best outcomes, Sensors must perform cryptographic operations, such as authenticating their data at the time of use. This “time check at use” ensures that sensor readings are trustworthy, preventing tampering or spoofing. 

Similarly, ML models stored in external flash memory and executed in-place (XIP) must be authenticated and decrypted during runtime to maintain system integrity.

Another strategy involves deploying analog sensors to monitor the security of the system itself. Voltage, temperature, electromagnetic, and light sensors can detect anomalies indicative of attacks, such as decapping a chip or injecting faults. 

However, these sensors introduce a recursive challenge: how to secure the sensors that protect the system. Ensuring the integrity of sensor circuitry requires robust design practices, such as tamper-resistant layouts and secure calibration mechanisms.

Emerging Solutions and Future Directions

Addressing analog security in multi-die systems and edge applications requires a combination of hardware, software, and system-level innovations. 

Below are some promising approaches:

1. Hardware Security Modules (HSMs) for Analog Chiplets

Integrating HSMs into analog chiplets can provide unique identifiers and cryptographic functions, enabling authentication and secure communication. This approach, advocated by Synopsys’ Koeter, ensures that each chiplet whether analog or digital can be trusted within the system.

2. Polymorphic Analog Circuits

Research into polymorphic circuits, such as those explored by DARPA, offers a novel way to enhance analog security. By designing circuits that change functionality based on operating conditions (e.g., voltage levels), engineers can create systems that are difficult to reverse-engineer or attack via side-channels. 

For instance, a circuit performing AES encryption at 1.5V and SHA hashing at 1.2V is inherently resistant to analysis, as its behavior depends on dynamic conditions.

3. System-Level Security Management

Treating each chiplet as a standalone, secure subsystem is key to multi-die security. A central system chiplet can act as a security manager, coordinating authentication, encryption, and monitoring across the system. This architecture supports “security islands,” where chiplets operate with different trust levels, enhancing overall resilience.

4. Advanced Packaging for Security

Advanced packaging techniques, such as 2.5D interposers or 3D stacking, can be leveraged to improve security. 

For example, embedding secure interconnects or tamper-detection mechanisms within the package can protect chiplet-to-chiplet communications. 

Additionally, as packaging costs decrease, more heterogeneous integration of analog components, such as RF or sensor chiplets, will become feasible.

5. Redundancy and Monitoring

In safety-critical applications, redundancy in analog sensors and continuous monitoring can mitigate risks. 

Aging counters, can adjust performance based on sensor degradation, while environmental sensors (e.g., for temperature or light) can detect physical attacks. These measures, however, must balance security with cost and power efficiency.

Implications for Industry and Research

The growing prominence of analog circuits in multi-die systems and edge applications has far-reaching implications for the semiconductor industry. 

Chipmakers must invest in analog security research, as the current focus on digital security is insufficient for heterogeneous designs. This includes developing new design methodologies, EDA tools tailored for analog security, and standards for chiplet interoperability and authentication.

The open chiplet marketplace, while promising, requires robust mechanisms to prevent counterfeit or malicious chiplets. 

Industry consortia, such as the Universal Chiplet Interconnect Express (UCIe), could play a role in defining security standards for chiplet-based systems. 

Additionally, collaboration between analog and digital design teams is essential to bridge the gap between these domains, ensuring that security is addressed holistically.

For researchers, analog security presents a rich field of inquiry. 

Topics such as side-channel-resistant analog designs, fault-tolerant sensor architectures, and secure analog-digital interfaces warrant further exploration. 

Government-funded initiatives, like DARPA’s work on asynchronous and polymorphic circuits, could accelerate progress in this area.

The transition to multi-die assemblies and the rising value of analog data at the edge are thrusting analog security into the forefront of semiconductor design. While multi-die systems enable greater flexibility and reuse of analog components, they also expose analog circuits to new vulnerabilities, from physical attacks to side-channel exploits. At the edge, the reliance on analog sensors for AI and IoT applications underscores the need to secure analog data and processing.

By integrating hardware security modules, exploring polymorphic circuits, and adopting system-level security management, the industry can address these challenges. However, this requires a concerted effort to advance analog security research, develop new design tools, and establish industry standards. As analog and digital domains converge in multi-die systems, ensuring the security of both is critical to realizing the full potential of next-generation electronics. The stakes are high, particularly in safety-critical applications like automotive and aerospace, where secure analog circuits are not just a technical necessity but a matter of life and death.