VLSI
VSIDE - VSDSP Integrated Development Environment
VLSI Solution has announced VSIDE - the Integrated Development Environment for VSDSP Processor Family. VSIDE is an inte…
Debugging
Verilog
Source Navigator for Verilog
Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many Verilog…
Test bench
Comit-TX Verilog Testbench Extractor
Comit-TX extracts a self-checking Verilog testbench of any module inside a design that has a system level testbench.…
Verdi
nECO for Verdi and Debussy debug systems
nECO is an integrated graphical netlist modification tool for the Verdi and Debussy debug systems. The Novas debug syst…
RTL
Functionally debug in RTL source using Identify RTL Debugger
The Identify RTL Debugger lets FPGA designers and ASIC prototyping designers to functionally debug their hardware direc…
Verification
The Art of Debugging: Make it Fail
"Debugging" is the most valuable engineering skills, not taught in any formal setting, and often learned the …