VHDL
VHDL Online resources
VHDL Books There are dozens of great books talking about VHDL modeling, simulation and synthesis. Here are some of the…
RTL
RTL
Functionally debug in RTL source using Identify RTL Debugger
The Identify RTL Debugger lets FPGA designers and ASIC prototyping designers to functionally debug their hardware direc…
Verification
Boosting RTL Verification with High-Level Synthesis
Instead of prolonging the painful process of finding bugs in RTL code, the design flow needs to be geared toward creati…
VHDL
Comparison of VHDL to Other Hardware Description Languages
VHDL Disadvantages VHDL is verbose, complicated and confusing Many different ways of saying the same thing Constructs t…
RTL
behavioral & RTL
Multi-cycle functionality: It is a fundamental characteristic of synthesizable RTL code that the complete functionality…
RTL
Latch Vs Flip Flop
A latch and a flip-flop are two basic building blocks in digital electronics used to store binary data. The main diffe…
RTL
Glitches, Hazards and Lizards
A glitch is a momentary error condition on the output of a circuit due to unequal path delays in a circuit. It is seen …
RTL
Glue Logic
glue logic is the circuitry needed to achieve compatible interfaces between two (or more) different off-the-shelf integ…
Verification
Application Specific Integrated Circuit ( ASIC )
An application-specific integrated circuit or ASIC comprises an integrated circuit (IC) with functionality customized f…