Verilog
Verilog2C++
Verilog2C++ is a Verilog to C++ translation program that translates a C++ class of a Verilog design using a cycle-ac…
EDA Tools
EDA Tools
Splint Annotation-Assisted Lightweight Static Checking
Splint is a tool for statically checking C programs for security vulnerabilities and coding mistakes. With minimal e…
Verilog
Source Navigator for Verilog
Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many Verilog…
Test bench
Comit-TX Verilog Testbench Extractor
Comit-TX extracts a self-checking Verilog testbench of any module inside a design that has a system level testbench.…
EquivalenceChecking
Incisive Conformal ASIC
With thousands of Tapeouts, Conformal ASIC is the most widely-supported equivalency checking tool in the industry. It&#…
Verdi
nECO for Verdi and Debussy debug systems
nECO is an integrated graphical netlist modification tool for the Verdi and Debussy debug systems. The Novas debug syst…
RTL
Functionally debug in RTL source using Identify RTL Debugger
The Identify RTL Debugger lets FPGA designers and ASIC prototyping designers to functionally debug their hardware direc…
Synopsys
Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route
Synopsys, Inc. has introduced Design Compiler 2010, the latest RTL synthesis innovation within the Galaxy™ Implementati…
Timing
Probabilistic Timing Analysis
Because of shrinking feature sizes and the decreasing faithfulness of the manufacturing process to design features, pro…
VN-Cover
EDA Tools - VN-Cover Emulator Coverage Analysis for HW Emulation
VN-Cover Emulator by TransEDA enables engineers to obtain coverage on their SoCs in a hardware-accelerated environment …
VN-Cover
EDA Tools - VN-Cover Coverage Analysis
VN-Cover by TransEDA is a code and FSM coverage tool that identifies any unverified parts of a simulated HDL design. VN…