The Digital Electronics Blog

C++

Verilog2C++

mg -4:56 PM BBC 1

EDA Tools

Splint Annotation-Assisted Lightweight Static Checking

mg -4:55 PM BBC 1

Debugging

Source Navigator for Verilog

mg -4:54 PM BBC 1

Debugging

Comit-TX Verilog Testbench Extractor

mg -4:53 PM BBC 1

EDA Tools

Incisive Conformal ASIC

mg -4:33 PM BBC 1

EDA Tools

System Architect for micro-architecture performance analysis and optimization during functional simulation

mg -4:32 PM BBC 1

Debugging

nECO for Verdi and Debussy debug systems

mg -4:31 PM BBC 1

Debugging

Functionally debug in RTL source using Identify RTL Debugger

mg -4:30 PM BBC 1

Debugging

Gatevision for Netlist debugging

mg -4:27 PM BBC 1

Design Compiler

Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route

Murugavel -7:49 AM BBC 1

DFM

Probabilistic Timing Analysis

Murugavel -3:32 PM BBC 1

Coverage Analysis

EDA Tools - VN-Cover Emulator Coverage Analysis for HW Emulation

mg -3:47 PM BBC 1

Coverage Analysis

EDA Tools - VN-Cover Coverage Analysis

mg -3:44 PM BBC 1