Showing posts with label Design. Show all posts
Showing posts with label Design. Show all posts

We are now blog.digitalelectronics.co.in


We have a new look and feel to the articles that you loved most :-)



Your favorite blog, digitalelectronics.blogspot.com is now blog.digitalelectronics.co.in. Those who have already visited this blog since yesterday would have noticed a much simpler clutter free appearance while keeping the legacy features. We’ve refined the design and encapsulated the information accumulated over the years into an easily digestible and navigatable website. I am quite proud of it. In the coming months, i hope to improving this blog further so that it best serves you, the blog members.
Thank you.

Best known modelling practices for gigabit serial design - Live Webcast


This presentation will go over some of the common issues encountered when setting up performing circuit simulation of high speed serial designs. Topics will include s-parameter passivity and causality, frequency sampling and bandwidth and how they relate to simulation accuracy, model concatenation, and correlation between the time and frequency domains.

This webcast is Hosted by EDN and Sponsored by ANSYS.

Register Now - Click Here

Presenter:
Daniel Dvorscak,
Senior Application Engineer,ANSYS, Inc.

Date: March 25, 2011
Time: 3:00 PM ET / 12:00 PM PT

VSIDE - VSDSP Integrated Development Environment


VLSI Solution has announced VSIDE - the Integrated Development Environment for VSDSP Processor Family. VSIDE is an integrated development environment for VLSI Solution's 16/40-bit VSDSP digital signal processor family. It contains a complete set of development utilities, including an optimizing ANSI-C compiler, assembler, linker, profiler, etc. All programs are integrated into a simple-to-use, easy-to-learn package running on a PC / Windows XP or Vista platform.

VSIDE supports emulator-based debugging using real hardware. It also contains several example projects to help users get easily started. The beta version of the tool has been successfully used in the development of many audio products such as echo cancellation for Skype phone and pitch shifting of the audio source for a portable karaoke product. DSPeaker's (www.dspeaker.com) award winning Anti-Mode™ algorithm was debugged in a short time by using the powerful tools of VSIDE.

VSIDE currently supports VLSI Solution's audio codec chip VS1053 as well as VLSI's all-new digital signal processor circuit VS8053. Support for the low cost VS1000 audio system chip will be added by Q1/2011. VLSI Solution's current programming examples will gradually be ported to VSIDE.

Keeping with the spirit of VLSI Solution's openness policy, VSIDE can be downloaded for free at: http://www.vlsi.fi/en/support/software/vside.html

About VLSI Solution
VLSI Solution is an innovative new technology creator that designs and manufactures integrated circuits. Within its 19 years of existence VLSI has build an extensive in-house IP library and has the capability to pull through complicated mixed-signal IC projects, ranging from digital audio to RF applications.

For more information, see http://www.vlsi.fi/

Driving Flexibility into Automotive Electronics Design


With the dramatic increase in development costs for state-of-the-art process technologies, such as next-generation automotive electronic systems, specialization of traditional microcontrollers no longer makes business sense. This white paper discusses a process to develop an exact microcontroller for a specific application by implementing it into an Altera Cyclone IV FPGA for prototyping and volume production. Verification, software development, and field testing can be done immediately after design or even in parallel.

Data Management for Hardware Design Teams


Hardware design data and design flows present unique requirements that are not met by software configuration management systems. This paper outlines how a system designed from the ground up to meet the unique requirements of hardware designers manages composite design objects, integrates into industry-standard design flows, understands design hierarchy, optimizes disk space usage for very large files, and facilitates collaboration across multiple sites.

Dark side of design reviews


Choose your words with care, phrases like "…will never work", "…is useless" etc. will spoil your cooperation with the designer(s) far beyond your current project.

Never count the number of points in your feedback to the designer, or even worse return him pages of long numbered lists. Never consequently call your points for design "errors". If you need to be able to refer to the points on your lists use alphabetically numbered lists. You don't get paid for proving the incompetence of the designer but for improving the quality of the final product, thereby saving your company thousands of dollars.

Remember: The designer is not stupid - Engineers make a lot of errors when they are experienced and know for sure - and take things for granted.

If you try to insist or convince the designer of your point of view you will very soon have an enemy among your colleagues at work. By giving him a less emphasized feedback his responsibility and curiosity makes him pick up the important points in your feedback and at the end of the day you "save his ass" and get a friend.

Design review meetings are not a modern pillory. Only designer(s) and reviewer(s), all working on the project, should attend the meeting.

Basic aspects of a typical digital design flow...


  • Requirements
    • Description of what the customer wants
  • Algorithm
    • Functional description of computation. Probably not synthesizable. Could be a flowchart, software, diagram, mathematical equation, etc..
  • High-Level Model
    • HDL code that is not necessarily synthesizable, but divides algorithm into signals and clock cycles. Possibly mixes datapath and control. In VHDL, could be a singleprocess that captures the behaviour of the algorithm. Usually synthesizable; resulting hardware is usually big and slow compared to optimized RTL code.
  • Dataflow Diagram
    • A picture that depicts the datapath computation over time, clock-cycle by clock-cycle.
  • Hardware Block Diagram
    • A picture that depicts the structure of the datapath: the components and the connections between the components. (e.g., netlist or schematic)
  • State Machine
    • A picture that depicts the behaviour of the control circuitry over time.
  • DP+Ctrl RTL code
    • Synthesizable HDL code that separates the datapath and control into separate processes and assignments.
  • Optimized RTL Code
    • HDL code that has been written to meet design goals (high performance, low power, small, etc.)
  • Implementation Code
    • A collection of files that include all of the information needed to build the circuit: HDL program targeted for a particular implementation technology (e.g.a specificFPGA chip), constraint files, script files, etc.

Note: Recomendation Spend the time up front to plan a good design on paper. Use dataflow diagrams and state machines to predict performance and area. You will probably produce a more optimal design with less effort if you explore high-level optimizations with dataflow diagrams and state machines.

A nice site for basics on Digital Logic Design


http://www.allaboutcircuits.com/, Look up Volume IV - Digital

Summary of topics covered...

Chapter 1: NUMERATION SYSTEMS
Chapter 2: BINARY ARITHMETIC

Chapter 3: LOGIC GATES

Chapter 4: SWITCHES

Chapter 5: ELECTROMECHANICAL RELAYS

Chapter 6: LADDER LOGIC

Chapter 7: BOOLEAN ALGEBRA

Chapter 8: KARNAUGH MAPPING

Chapter 9: COMBINATIONAL LOGIC FUNCTIONS
Chapter 10: MULTIVIBRATORS
Chapter 11: COUNTERS

Chapter 12: SHIFT REGISTERS

Chapter 13: DIGITAL-ANALOG CONVERSION

Chapter 14: DIGITAL COMMUNICATION

Chapter 15: DIGITAL STORAGE (MEMORY)

Chapter 16: PRINCIPLES OF DIGITAL COMPUTING

Phase locked loop (PLL)


PLL stands for 'Phase-Locked Loop' and is basically a closed loop frequency control system, whose functioning is based on the phase sensitive detection of phase difference between the input and output signals of the controlled oscillator (CO).

For further info, click on the title...

NAND or NOR design


NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate.

Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND ( the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance pmos's are in series connection which again increases the resistance).

FPGA & ASIC based design


The main diferrence between ASIC and FPGA based design is in the Back-end.
In FPGAs there is not much activities in back end.

FPGA flow:
SPECIFICATION -> RTL DESIGN -> FUNCTIONAL SIMULATION -> SYNTHESIS -> TRANSLATION -> MAPPING -> PLACE & ROUTE -> BITGEN GENERATION -> DOWNLOAD TO THE CHIP.

ASIC flow:
SPECIFICATION -> RTL DESIGN -> FUNCTIONAL SIMULATION -> SYNTHESIS -> EXTRACT RC VALUES -> DRC, LVS,etc., -> LIBRARY VENDOR SPECIFIC FILE FORMAT

Coarse and Fine grained architectures


Coarse-grained architectures consist of fairly large logic blocks, often containing two or more look-up tables and two or more flip-flops. In a majority of these architectures, a four-input look-up table (think of it as a 16x1 ROM) implements the actual logic. The larger logic blocks usually corresponds to improved performance.

Fine-grained circuits, consist of the basic cell being simple (OR, AND,and NOT).

"Latch" Vs "Flip Flop"


Welcome to the most popular title on this Blog ;-))))) !!!


A flip-flop is Edge sensitive: Output only changes on rising (or falling) edge of clock.
A latch is Level sensitive: Output changes whenever clock/Enable is high (or low)

A common implementation of a flip-flop is a pair of latches (Master/Slave flop).

Latches are sometimes called “transparent latches”, because they are transparent (input directly connected to output) when the clock is high.

The clock to a latch is primarily called the “enable”.

For more information have a look at the picture below.








Deprecated Hardware:

Latches:
  1. Use flops, not latches
  2.  Latch-based designs are susceptible to timing problems
  3. The transparent phase of a latch can let a signal “leak” through a latch — causing the signal to affect the output one clock cycle too early
  4. It’s possible for a latch-based circuit to simulate correctly, but not work in real hardware, because the timing delays on the real hardware don’t match those predicted in synthesis
Flip-flops:
  1. Limit yourself to D-type flip-flops
  2. Some FPGA and ASIC cell libraries include only D-type flip flops. Others, such as Altera’s APEX FPGAs, can be configured as D, T, JK, or SR flip-flops.

  • For every signal in your design, know whether it should be a flip-flop or combinational. Examine the log file e.g. dc shell.log to see if the flip-flops in your circuit match your expectations, and to check that you don’t have any latches in your design.
  • Do not assign a signal to itself (e.g. a <= a; is bad). If the signal is a flop, use an enable to cause the signal to hold its value. If the signal is combinational, then assigning a signal to itself will cause combinational loops, which are very bad.
If you are looking for code snippets for following types of harware, please leave a comment.
  1. Flops with Waits and Ifs
  2. Flops with Synchronous Reset
  3. Flops with Chip-Enable
  4. Flops with Chip-Enable and Mux on Input
  5. Flops with Chip-Enable, Mux's, and Reset

Glitches, Hazards and Lizards


A glitch is a momentary error condition on the output of a circuit due to unequal path delays in a circuit. It is seen as an additional pulse or pulses on the output. Between a time the input signals are settled and the output signals are being established a glitch can occur if there is an hazard(functional or logical).

Glitches due to functional errors can occur when two input signals or more change in values at the same time. It is related to the function that is being implemented and cannot be removed by adding extra circuit.

Glitches due to logical hazard can occur only when one i/p signal changes it value. A logic hazard can be removed by add extra circuit. A logic hazard can be static or dynamic.

Low power design


Primarily design for low power depends on the characteristics design being accomplished. If it is a multi-million gate design we cannot implement any technique that is gate specific, it has to be a global technique.
  1. Multi-Vdd, variable Vdd and Multi-Vth seems to be a good global solution.
  2. Reducing the clock speed will result in low power consumption, but on the cost of performance.
  3. Using power headers and power footer transistors on logic gates cuts down power.
  4. You could separate the design in blocks, which can go in to sleep mode.
  5. Another solutions is variable VDD and variable frequency (as Intel or AMD do).This means, you adapt VDD and frequency to the necessary performance.
  6. Gated clocks and Logic Addressable clocks, dis adv - timing problems due to improper latching of signals, and difficult to test.
  7. -ve edge triggered flops, (nor+inv) = 1.5 gates, +ve edge triggered flops, (and+inv) = 2.5 gates, so -ve has less gates, less glitching and hence low power.

Any more thoughts and ideas are welcome.

Glue Logic


glue logic is the circuitry needed to achieve compatible interfaces between two (or more) different off-the-shelf integrated circuits.

An example of glue logic is the address decoder which with older processors like the 6502 or Z80 had to be added externally to divide up the addressing space of the processor into RAM, ROM and I/O. Newer versions of the same processors (such as the WDC 65816 or Zilog eZ80) instead have internal address decoders so glueless interfacing to the most common external devices becomes possible.

Sometimes, glue logic is used to encrypt the proprietary electronics circuitry by the vendor and to prevent the product from being illegally counterfeited.

Application Specific Integrated Circuit ( ASIC )


An application-specific integrated circuit or ASIC comprises an integrated circuit (IC) with functionality customized for a particular use (equipment or project), rather than serving for general-purpose use.

For example, a chip designed solely to run a cash register is an ASIC. In contrast, a microprocessor is not application-specific, because users can adapt it to many purposes.

The initial ASICs used gate-array technology.

The British firm Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customisation occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customised by both metal and polysilicon layers. Some base dies include RAM elements.

In the late 1980s, the availability of logic synthesis tools (such as Design Compiler) that could accept hardware description language descriptions using Verilog and VHDL and compile a high-level description into to an optimised gate level netlist brought "standard-cell" design into the fore-front. A standard-cell library consists of pre-characterized collections of gates (such as 2 input nor, 2 input nand, invertors, etc.) that the silicon compiler uses to translate the original source into a gate level netlist. This netlist is fed into a place and route tool to create a physical layout. Routing applications then place the pre-characterized cells in a matrix fashion, and then route the connections through the matrix. The final output of the "place & route" process comprises a data-base representing the various layers and polygons in GDS-II format that represent the different mask-layers of the actual chip.

Finally, designers can also take the "full-custom" route in implementing an ASIC. In this case, an individual description of each transistor occurs in building the circuit. A "full-custom" implementation may function five times faster than a "standard-cell" implementation. The "standard-cell" implementation can usually be implemented quite a bit quicker and with less risk of errors, than the "full-custom" choice.

As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) has increased from 5000 gates to 20 million or more. Modern ASICs often include 32-bit processors and other large building-blocks. Many people refer to such an ASIC as a SoC - System on a Chip.

The use of intellectual property (IP) in ASICs has become a growing trend. Many ASIC houses have had standard cell libraries for years. However IP takes the reuse of designs to a new level. Designers of most complex digital ICs now utilise computer languages that describe electronics rather than code. Many organizations now sell tested functional blocks written in these languages. For example, one can purchase CPUs, ethernet or telephone interfaces.

For smaller designs and/or lower production volumes, ASICs have started to become a less attractive solution, as field-programmable gate arrays (FPGAs) grow larger, faster and more capable. Some SoCs consist of a microprocessor, various types of memory and a large FPGA.

So having said, this blog is dedicated to Digital Electronics, VLSI, ASICs, SOCs etc.