The main diferrence between ASIC and FPGA based design is in the Back-end.
In FPGAs there is not much activities in back end.
FPGA flow:
SPECIFICATION -> RTL DESIGN -> FUNCTIONAL SIMULATION -> SYNTHESIS -> TRANSLATION -> MAPPING -> PLACE & ROUTE -> BITGEN GENERATION -> DOWNLOAD TO THE CHIP.
ASIC flow:
SPECIFICATION -> RTL DESIGN -> FUNCTIONAL SIMULATION -> SYNTHESIS -> EXTRACT RC VALUES -> DRC, LVS,etc., -> LIBRARY VENDOR SPECIFIC FILE FORMAT
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Hi I would like to restate the ASIC flow mentioned above .
ReplyDeleteSPEC -> RTL -> FUNC. VERIF -> SYNTHESIS -> FORMAL VERIFICATION -> BACKEND ( floor plan , P&R , CTS ) -> FORMAL VERIFICATION -> POST LAYOUT STA -> LVS / DRC -> TAPEOUT
Thanks Andy. It is indeed more accurate.
ReplyDeleteThanks for info
ReplyDeleteThanks for info .............
ReplyDeleteCorrection to the FPGA flow:
ReplyDeleteSPECIFICATION -> RTL DESIGN -> FUNCTIONAL SIMULATION -> Constraints and Floorplan -> SYNTHESIS -> TRANSLATION -> MAPPING -> PLACE & ROUTE -> BITGEN GENERATION -> DOWNLOAD TO THE CHIP.
Bring it on!
ReplyDelete