Showing posts from 2005

Asynchronous in a synchronous world - Part 2

Asynchronous in a synchronous world - Part 1

Asynchronous in a synchronous world - Introduction

Verilog code to detect if a 64bit pattern can be expressed using power of 2

Verilog Shift Register with Test Bench

Verilog Awareness

Verilog Awareness

Clock Jitter

Verilog Blocking Vs Non Blocking, Myths and Facts

Clock tree synthesis

Design Guidelines and Criteria for Digital Electronics

"Safe" and "Unsafe" state machines

Metastability

Synthesizable Verilog from behavioral constructs - 5

Synthesizable Verilog from behavioral constructs - 4

synthesizable Verilog from behavioral constructs - 3

synthesizable Verilog from behavioral constructs - 2

synthesizable Verilog from behavioral constructs - 1

Matters

A nice site for basics on Digital Logic Design

1's complement and 2's complement

negative setup and hold time

I2C Questions

more questions

Mux out of an XOR

Some recent interview questions

Glitch in a combinational circuit and the way to avoid that.

Why "FOR LOOP" is not advisable

Setup Time & Hold Time - By popular demand

Logic Density

Negative hold time

Test

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