Showing posts from 2005
Synchronization

Asynchronous in a synchronous world - Part 2

byMG - BBC 1
Synchronization

Asynchronous in a synchronous world - Part 1

byMG - BBC 1
Synchronization

Asynchronous in a synchronous world - Introduction

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Coding

Verilog code to detect if a 64bit pattern can be expressed using power of 2

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Coding

Verilog Shift Register with Test Bench

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Coding

Verilog Awareness

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Coding

Verilog Awareness

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Jitter

Clock Jitter

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Coding

Verilog Blocking Vs Non Blocking, Myths and Facts

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Synthesis

Clock tree synthesis

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Coding

Design Guidelines and Criteria for Digital Electronics

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State Machines

"Safe" and "Unsafe" state machines

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Metastability

Metastability

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Interview Questions

Synthesizable Verilog from behavioral constructs - 5

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Interview Questions

Synthesizable Verilog from behavioral constructs - 4

byMG - BBC 1
Interview Questions

synthesizable Verilog from behavioral constructs - 3

byMG - BBC 1
Interview Questions

synthesizable Verilog from behavioral constructs - 2

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Interview Questions

synthesizable Verilog from behavioral constructs - 1

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Updates

Matters

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Design

A nice site for basics on Digital Logic Design

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Learning

1's complement and 2's complement

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Hold

negative setup and hold time

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I2C

I2C Questions

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Interview Questions

more questions

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mux

Mux out of an XOR

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Interview Questions

Some recent interview questions

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Glitch

Glitch in a combinational circuit and the way to avoid that.

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For Loop

Why "FOR LOOP" is not advisable

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Hold

Setup Time & Hold Time - By popular demand

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Logic Density

Logic Density

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Hold

Negative hold time

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TOC

Test

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