more questions

1. Given 2 4 bit nos, A= 1001, b= 1100
  • HOW DO YOU ExOR THEM using minimum number of gates?
  • how do you nand them?
  • how do your or them?
2. given a 4:1 functional generator how do you resolve a 5:1 functional generator using only 4:1 funtional generators? what happens to the unused inputs?

3. using a 4:1 mux how many 4:1 mux do you need to design a 8:1 mux?

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  1. Interview questions at cisco.

    1. In order to find out stack fault of a three input nand gate how many necessary input vectors are needed ?
    2. What is parity generation ?
    3. A nand gate becomes ___ gate when used with negative logic ?
    4. What is the advantage of cmos over nmos ?
    5. What is the advantage of synchronous circuits over asynchronous circuits ?
    6. What is the function of ALE in 8085 ?
    7. A voice signal sample is stored as one byte. Frequency range is 16 Hz to 20 Hz. What is the memory size required to store 4 minutes voice signal?
    8. What will the controller do before interrupting CPU?
    9. In a normalized floating point representation, mantissa is represented using 24 bits and exponent with 8 bits using signed representation. What is range ?
    10. The stack uses which policy out of the following– LIFO, FIFO, Round Robin or none of these ?
    11. Where will be the actual address of the subroutine is placed for vectored interrupts?
    12. Give the equivalent Gray code representation of AC2H.
    13.What is the memory space required if two unsigned 8 bit numbers are multiplied ?
    14. The vector address of RST 7.5 in 8085 processor is _______.
    15. Subtract the following hexadecimal numbers— 8416 - 2A16
    16. Add the following BCD numbers— 1001 and 0100
    17. How much time does a serial link of 64 Kbps take to transmit a picture with 540 pixels.
    18. Give the output when the input of a D-flip flop is tied to the output through the XOR gate.
    19. Simplify the expression AB + A( B + C ) + B ( B + C )
    20. Determine the logic gate to implement the following terms–ABC, A+B+C
    21. Implement the NOR gate as an inverter.
    22. What is the effect of temperature on the Icb in a transistor
    23. What is the bit storage capacity of a ROM with a 512*4 organization?
    24. What is the reason of the refresh operation in dynamic RAM’s ?
    25. Suppose that the D input of a flip flop changes from low to high in the middle of a clock pulse. Describe what happens if the flip flop is a positive edge triggered type?
    26. How many flip flops are required to produce a divide by 32 device ?
    27. An active HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?
    28. Implement the logic equation Y = C^BA^ + CB^A + CBA with a multiplexer.
    (where C^ stands for C complement)
    29. Equivalent Gray code representation of AC2H.
    30. What does a PLL consist of ?

  2. Must Know Question

    1. Setup Time and Hold Time:
    * What is it ?
    * How do you solve the setup and hold time issues ?
    * What are the factors that affect them ?
    * Does changing the clock period affect setup/hold issues ? Why or why not ?

    2. ASIC Design Flow/FPGA Design Flow:
    * Flow from spec to gds
    * Understand the Inputs/Outputs at each stage of the flow
    * Question will be related to the projects/design you have done

    3. Clock Related Stuff:
    * Clock Skew
    * Clock Trees
    * Clock Latency
    * Clock Insertion Delay
    * Clock Period
    * Clock Trees
    * Max Clock Frequency
    * Glitch ? What, Why and How to avoid it ?
    * Useful Skew
    * Effective Skew
    * Clock Buffers ? How are they different from regular buffers ?

    Synthesis Basic Questions

    1. Describe a basic Synthesis Flow ?

    2. Four Different Path Groups
    * Input to Register
    * Register to Register
    * Register to Output
    * Input to Output

    3. What are wireload models ?
    * Different Types of wireload Models
    * Where they help and where they are inadequate
    * What are default wireload models and what are custom wireload models

    4. Scan Insertion
    * Scan and IDDQ testing


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