Setup Time and Hold Time: Equations, Examples and Fixes

Setup time is how long the data input of a flip-flop must be stable before the active clock edge; hold time is how long it must stay stable after that edge. Static timing analysis checks setup against the slowest path and the clock period, and checks hold against the fastest path, with no clock period involved. This post gives both equations with a stated skew convention, works through numeric examples, and keeps the original answers on how setup and hold violations are fixed.

Key takeaways

• Setup check (same-edge, single-cycle path): T >= tcq,max + tcomb,max + tsetup - tskew.
• Hold check: tcq,min + tcomb,min >= thold + tskew.
• Skew here is capture clock arrival minus launch clock arrival. Positive skew helps setup and hurts hold.
• Setup depends on frequency; hold does not, as long as launch and capture use the same clock edge.
• Setup violations are usually harder to fix than hold violations, but either one can cause a respin.

Definitions

• Setup time (tsetup or tsu): the minimum time the D input must be stable before the active clock edge for the flip-flop to capture it reliably.
• Hold time (thold or th): the minimum time the D input must remain stable after the active clock edge.
• Clock-to-Q delay (tcq): time from the clock edge to a valid output. It has a maximum (tcq,max, used for setup) and a minimum (tcq,min, used for hold).
• Combinational delay: tcomb,max is the slowest path through the logic between two flops (propagation delay); tcomb,min is the fastest path (contamination delay).

Together, setup and hold define a small window around the clock edge in which D must not change. If D changes inside that window, the flop may capture the wrong value or go metastable.

The setup and hold window as a timing table

Time relative to the capturing clock edge	Requirement on D
Earlier than -tsetup	D may change freely
From -tsetup to 0 (the edge)	D must be stable (setup window)
From 0 to +thold	D must be stable (hold window)
Later than +thold	D may change freely

The setup check

Take a launching flop FF1 and a capturing flop FF2, both on the same rising clock edge with period T. In this post:

tskew = clock arrival at FF2 (capture) minus clock arrival at FF1 (launch).

Data launched by FF1 at one edge must reach FF2 at least tsetup before the next edge at FF2:

tcq,max + tcomb,max + tsetup <= T + tskew

so  T >= tcq,max + tcomb,max + tsetup - tskew

setup slack = (T + tskew - tsetup) - (tcq,max + tcomb,max)

Positive skew gives the data extra time, so it is subtracted from the minimum period. Clock uncertainty (jitter and margin) is normally subtracted from the required time as well; it is left out here to keep the numbers clear.

Worked example: setup and maximum frequency

Quantity	Value
Clock period T	2.00 ns (500 MHz)
tcq,max of FF1	0.15 ns
tcomb,max	1.50 ns
tsetup of FF2	0.10 ns
tskew	+0.05 ns (FF2 clock later)

1. Arrival time at FF2: 0.15 + 1.50 = 1.65 ns.
2. Required time: 2.00 + 0.05 - 0.10 = 1.95 ns.
3. Setup slack: 1.95 - 1.65 = +0.30 ns. The path passes.
4. Minimum period: 0.15 + 1.50 + 0.10 - 0.05 = 1.70 ns, so the maximum frequency for this path is 1 / 1.70 ns, about 588 MHz.

The hold check

For hold, the data launched by FF1 at an edge must not reach FF2 before FF2 has finished holding the previous data for that same edge:

tcq,min + tcomb,min >= thold + tskew

hold slack = (tcq,min + tcomb,min) - (thold + tskew)

T does not appear, which is the reason hold is frequency independent for same-edge paths.

Worked example: hold, then a skew change

Quantity	Value
tcq,min of FF1	0.10 ns
tcomb,min	0.03 ns
thold of FF2	0.05 ns
tskew	+0.05 ns

1. Earliest arrival: 0.10 + 0.03 = 0.13 ns. Requirement: 0.05 + 0.05 = 0.10 ns. Hold slack = +0.03 ns. Passes.
2. After clock tree synthesis the skew grows to +0.12 ns. Requirement: 0.05 + 0.12 = 0.17 ns. Hold slack = -0.04 ns. Fails.
3. Adding a hold buffer with a minimum delay of 0.06 ns gives arrival 0.19 ns and hold slack +0.02 ns. Its maximum delay is added to the setup path too, so recheck setup.

Fixing setup and hold violations: the original answers

This post was first written in reply to readers' questions on fixing setup violations with buffers, how hard hold fixing is, and which of the two matters more. Those answers follow, with light corrections to spelling.

a) Fixing setup violations

Generally speaking SETUP fixing is always DIFFICULT. This can be resolved by inserting buffers (as you mentioned) only in cases where the SETUP violation is because of large load/slew violations which causes huge delays in combinatorial blocks. Say there is an AND gate which is driving much more loads than it should and you see A to Y delay for that 3ns. Now this load violation can be fixed by adding a buffer after the AND gate and you may see now the AND gate has only 1.5ns and BUFFER added 0.3ns. Thus you gain 1.8ns in data path. To see if load/slew violations are causing your SETUP failure see report_timing with -cap -tran (assuming you annotate set_load or SPEF file also while doing STA). But if load/slew is NOT the culprit, then it is indeed tough to fix SETUP and you may need to revisit the logic structure between the flops.

Editor's note (November 2026): in the example above the AND gate plus buffer now take 1.5 + 0.3 = 1.8 ns, so the net saving on the path is 3.0 - 1.8 = 1.2 ns. In current tools the full option names are -capacitance and -transition_time, which most tools accept in the shortened form shown.

b) Fixing hold violations

HOLD fixing is comparatively far easy. Simply by adding buffers in the data path. There are lots of automated scripts and even DC can do that with -fix_hold. This is generally done at the last stage after the CLK routing has been done.

Editor's note (November 2026): in Synopsys Design Compiler the usual form is the set_fix_hold command on the clock, followed by a compile. Hold fixing today is mostly done in the place and route tool after clock tree synthesis, when real skew is known.

c) Which is more important?

I would say both are equally IMPORTANT and any one of them is sufficient enough to cause a RESPIN :-(

Finally the MOST important thing to remember always is SETUP is frequency dependent, while HOLD is NOT!

Note: This is generally true if you use only +ve edge clocking. If you mix both +ve and -ve edges in your design, then hold time also has a frequency dependency.

Why mixed-edge paths make hold depend on frequency

The note above deserves a worked case. Take a path launched on the rising edge at time 0 and captured on the falling edge, with a 50% duty cycle and zero skew.

• Setup is checked against the falling edge at T/2: tcq,max + tcomb,max + tsetup <= T/2. Only half a cycle is available.
• Hold is checked against the falling edge one cycle earlier, at T/2 - T = -T/2: tcq,min + tcomb,min >= thold - T/2. The half period appears in the equation, so hold now depends on T.

With T = 2 ns the hold requirement is thold - 1 ns, which is easy to meet. As T shrinks the margin shrinks with it. The reverse case, falling-edge launch and rising-edge capture, behaves the same way: hold gains T/2 of margin.

Setup versus hold at a glance

	Setup	Hold
Path checked	Slowest (max delays)	Fastest (min delays)
Capture edge	Next edge after launch	Same edge as launch
Depends on clock period	Yes	No, for same-edge paths
Effect of positive skew	Helps	Hurts
Worst corner, typically	Slow process, low voltage	Fast process, high voltage
Fix on silicon	Lower the frequency	Usually none; needs a respin
Typical design fixes	Restructure logic, upsize, buffer heavy loads, pipeline, useful skew	Insert delay buffers, reduce skew

How interviewers extend this question

• "Derive the maximum frequency of this path." Use the setup equation and solve for T, as in the worked example.
• "What happens with clock skew?" State your sign convention first, then show that positive skew helps setup and hurts hold.
• "Can hold time be negative?" Yes, see the post on negative hold time linked below.
• "Why is a shift register a hold risk?" There is no logic between the flops, so tcomb,min is about zero.

Related reading

• Contamination delay and why it decides hold time
• Negative hold time explained with a worked example
• Setup slack and hold slack in static timing analysis
• Inverters and buffers in STA and timing closure
• The Semiconductor Hub glossary: setup time and clock skew

Frequently asked questions

What is the difference between setup time and hold time?

Setup time is the stable period required before the clock edge; hold time is the stable period required after it. Setup is checked on the slowest path, hold on the fastest path.

Why is hold time independent of clock frequency?

For a same-edge path the hold check compares data launched and captured on the same clock edge, so the period cancels out of the equation.

How does clock skew affect setup and hold?

With skew defined as capture clock minus launch clock, positive skew adds time for setup and removes the same amount from the hold margin. Negative skew does the opposite.

How do you fix a setup violation?

Reduce the path delay: restructure or pipeline the logic, upsize drivers, buffer heavily loaded nets, use faster cells, or move clock edges with useful skew. If none of these is enough, lower the target frequency.

How do you fix a hold violation?

Add delay on the short path with buffers or delay cells, or reduce the skew between the clocks. Check that the added delay does not create a setup violation.