Glitch in a combinational circuit and the way to avoid that.

A glitch resistive transition means, it is not possible to have any intermediate momentary values during output transition.

Consider the final logic gate in the below design, which is driving the output "O", "D" ns is propagation delay of the gate

D
d1 _____________
I1 -------| Final Logic |
|| Gate |--------- O
I2 -------|_____________|
d2
logic & routing delay of I1 = d1
logic & routing delay of I2 = d2
Say d1 > d2; Skew d = d1-d2

Case 1:
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No skew between the inputs I1 & I2 (d1 = d2)
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* There will not be any GLITCHES at output.
* Output will be ready after D ns from an input change.

Case 2:
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There is a skew "d" ns between the inputs I1 & I2 (the difference in logic and routing delay from the driving point cause the skew) (d1 != d2)
* Output will be settled after "d+D" ns from an input change.
* Outputs at "D to d+D" ns from an input change can have momentry unwanted vales (GLITCHES)

Solution 1
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Keep the skew between the inputs as zero (no skew) for the output driving logic gate (Similar to Case 1).
Solution 2
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Register the combinational output, so that the stable output can sample and hold it until an another stable output comes.
Register "O" with a sampling period "T" ns such that {d1 + D + Tsetup(of flip flop)} < T