synthesizable Verilog from behavioral constructs - 2

Modifying a behavioural Verilog while statement to make it synthesizable.


Behavioural:

command1;
while (x != 0)
begin
command2;
end
command3;

Synthesizable:

case (state)
0 : begin
command1;
if (x != 0)
begin
command2;
state <= 1;
end
else command3;
end

1 : if (x != 0)
begin
command2;
end
else command3;
endcase

Again, if a cycle delay between command1 and the other commands executing is acceptable, simpler code is the following:

case (state)
0 : begin
command1;
state <= 1;
end

1 : if (x != 0)
begin
command2;
end
else command3;
endcase



Note: in general commandi refers to a block of commands. It is assumed there is an
appropriate clock for the case statement state machines.
Care is required in setting appropriate reset states, initialization, and completion of use of a
state machine:

o Is there a signal to tell the state machine to begin?
o Does a done signal go high, signalling the state machine has finished?
o When it is not in operation, does the state machine idle correctly? Does it change signal values shared with other code? Does it set outputs from it to appropriate idling values?
o Is the state machine reset to the idle state by a reset signal?
o Ensure that you initialize all registers.
o Ensure that your state register has the correct bit width - if it is too small, assigning a larger state value will just return it to an earlier state.

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