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Showing posts with the label HDLC

HDLC

HDLC (High-level Data Link Control)

One Nanometer (Name changed) -8:20 PM BBC 1

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ModelSim PE Student Edition - Free HDL Simulation

2:50 PM BBC 3

Transport delay / Inertial Delay

5:13 PM BBC 3

Digital "Greatest Common Divisor (GCD)" - Euclid’s algorithm

7:08 PM BBC 3

Soft Macro Vs Hard macro?

5:50 PM BBC 3

Some good Puzzles / Interview questions

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A crash course in GSM, GPRS, EDGE, UMTS, HSPA, LTE and WiMax

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Memories - Test Patterns & Algorithms - Part 3

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Unit delay simulation - an intermediate step in Gate level simulation!

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Non-Synthesizable VHDL Code

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Verilog Shift Register with Test Bench

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