In this video Paul Otellini lays out the current state of Intel's silicon operations to shareholders at the company's annual Investor Day in Santa Clara.
Showing posts with label News. Show all posts
Showing posts with label News. Show all posts
Researchers Create Logic Circuits From DNA
Researchers at Duke University recently used DNA to craft tiny chips used in computers and electronic circuits. By mixing DNA snippets with other molecules and exposing them to light, researchers created self-assembling, DNA-based logic circuits. Once perfected the tech could serve as an endlessly abundant, cheap alternative to silicon semiconductors. Chris Dwyer, lead researcher on the project, says that one grad student using DNA to make self-assembling circuits could produce more logic circuits in one day than the global silicon chip industry can create in an entire month!"
Gawker Media received no direct revenue from iPhone 4G scoop
In response to the iPhone 4g post i ran yesterday i got quite a few comments and i want to highlight one of them specifically! One of our readers Simon Owens got a chance recently to interview Gawker's Nick Denton and found out that despite the fact that he paid $5,000 to the people who found the iPhone, Gawker Media received no direct revenue from those millions of pageviews it received from publishing the scoop.
Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route
Synopsys, Inc. has introduced Design Compiler 2010, the latest RTL synthesis innovation within the Galaxy™ Implementation platform, which delivers a two-fold speed-up in the synthesis and physical implementation flow.
To meet aggressive schedules for increasingly complex designs, engineers need an RTL synthesis solution that enables them to minimize iterations to speed up physical implementation. To address these challenges, topographical technology in Design Compiler 2010 is being extended to produce "physical guidance" to Synopsys' flagship place-and-route solution, IC Compiler, tightening timing and area correlation to 5% while speed IC Compiler's placement phase by 1.5 times (1.5X). A new capability allows RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. In addition, Design Compiler's new scalable infrastructure tuned for multicore processors yields 2X faster synthesis runtimes on four cores. These new Design Compiler 2010 productivity improvements will be highlighted today by users at the Synopsys Users Group (SNUG) meeting in San Jose, California.
"Cutting design time and improving design performance are essential to keep our competitiveness in the marketplace," said Hitoshi Sugihara, Department Manager, DFM & Digital EDA Technology Development at Renesas Technology Corp. "With the new physical guidance extension to topographical technology we are seeing 5 percent correlation between Design Compiler and IC Compiler, up to 2X faster placement in IC Compiler and better design timing. We are adopting the new technology innovations in Design Compiler to minimize iterations while meeting our design goals in shorter timeframes."
To alleviate today's immense time-to-market pressures, Design Compiler 2010 extends topographical technology to further optimize its links with IC Compiler, tightening correlation down to 5%. Additional physical optimization techniques are applied during synthesis, and physical guidance is created and passed to IC Compiler, streamlining the flow and speeding placement in IC Compiler by 1.5X. Design Compiler 2010 also provides RTL designers access to IC Compiler's floorplanning capabilities from within the synthesis environment. With the push of a button, designers can perform what-if floorplan exploration, enabling them to identify and fix floorplan issues early and achieve faster design convergence.
"For the last few years, we have used Design Compiler's Topographical technology to find and fix design issues during synthesis to give us predictable implementation," said Shih-Arn Hwang, Deputy Director R&D Center at Realtek. "We see Design Compiler 2010 synthesis results closely correlating to physical results, while accelerating placement in IC Compiler by 1.5X. This tight correlation between synthesis and layout, along with faster runtimes, is exactly what we need for reducing iterations and significantly shortening design schedules in 65 nanometer and smaller process technologies."
Design Compiler 2010 includes a new, scalable infrastructure designed to deliver significant runtime speed-up on multicore compute servers. It employs an optimized scheme of distributed and multithreaded parallelization techniques, delivering an average of 2X faster runtime on quad-core compute servers while achieving zero deviation of the synthesis results.
"We've focused Design Compiler improvements on helping designers shorten design cycles and improve productivity," said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group. "Since the introduction of topographical technology, the impact of logic synthesis on accelerating design closure with physical implementation has grown significantly. Design Compiler 2010 continues this trend, delivering a significant decrease in iterations and reducing run times in physical implementation. We have achieved this while dramatically updating our software infrastructure to best utilize the latest microprocessor architectures."
To meet aggressive schedules for increasingly complex designs, engineers need an RTL synthesis solution that enables them to minimize iterations to speed up physical implementation. To address these challenges, topographical technology in Design Compiler 2010 is being extended to produce "physical guidance" to Synopsys' flagship place-and-route solution, IC Compiler, tightening timing and area correlation to 5% while speed IC Compiler's placement phase by 1.5 times (1.5X). A new capability allows RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. In addition, Design Compiler's new scalable infrastructure tuned for multicore processors yields 2X faster synthesis runtimes on four cores. These new Design Compiler 2010 productivity improvements will be highlighted today by users at the Synopsys Users Group (SNUG) meeting in San Jose, California.
"Cutting design time and improving design performance are essential to keep our competitiveness in the marketplace," said Hitoshi Sugihara, Department Manager, DFM & Digital EDA Technology Development at Renesas Technology Corp. "With the new physical guidance extension to topographical technology we are seeing 5 percent correlation between Design Compiler and IC Compiler, up to 2X faster placement in IC Compiler and better design timing. We are adopting the new technology innovations in Design Compiler to minimize iterations while meeting our design goals in shorter timeframes."
To alleviate today's immense time-to-market pressures, Design Compiler 2010 extends topographical technology to further optimize its links with IC Compiler, tightening correlation down to 5%. Additional physical optimization techniques are applied during synthesis, and physical guidance is created and passed to IC Compiler, streamlining the flow and speeding placement in IC Compiler by 1.5X. Design Compiler 2010 also provides RTL designers access to IC Compiler's floorplanning capabilities from within the synthesis environment. With the push of a button, designers can perform what-if floorplan exploration, enabling them to identify and fix floorplan issues early and achieve faster design convergence.
"For the last few years, we have used Design Compiler's Topographical technology to find and fix design issues during synthesis to give us predictable implementation," said Shih-Arn Hwang, Deputy Director R&D Center at Realtek. "We see Design Compiler 2010 synthesis results closely correlating to physical results, while accelerating placement in IC Compiler by 1.5X. This tight correlation between synthesis and layout, along with faster runtimes, is exactly what we need for reducing iterations and significantly shortening design schedules in 65 nanometer and smaller process technologies."
Design Compiler 2010 includes a new, scalable infrastructure designed to deliver significant runtime speed-up on multicore compute servers. It employs an optimized scheme of distributed and multithreaded parallelization techniques, delivering an average of 2X faster runtime on quad-core compute servers while achieving zero deviation of the synthesis results.
"We've focused Design Compiler improvements on helping designers shorten design cycles and improve productivity," said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group. "Since the introduction of topographical technology, the impact of logic synthesis on accelerating design closure with physical implementation has grown significantly. Design Compiler 2010 continues this trend, delivering a significant decrease in iterations and reducing run times in physical implementation. We have achieved this while dramatically updating our software infrastructure to best utilize the latest microprocessor architectures."
openPICUS project officially takes off
This brand new device is an wireless stack and application development platform put into one. It is intended to be smart and low cost to allow ideas to crossover the labs walls and to enter the real market. openPICUS as a hardware platform offers to students an opportunity to experience in their thesis an interaction with iPhone and Android. The first 50 pcs of the starter kit will be shipped for FREE to those who contribute with the best ideas to the project. This project advocates OPEN HARDWARE philosophy from the draft phase.
The main characteristics:
HARDWARE
CPU Microchip PIC 24F 16 bit 44 pins QFN 64K Flash 8K Ram)
Wireless (Bluetooth / Wi-Fi)
Power 5V or 3,3V
Main connections: UART, Digital Inputs, Digital Outputs, Analog Inputs, PWMs, SPI display, I2C
Connector: 26 Ways IDC header (male) suitable for TH mounting or flat cable
SMT: 26 Pins for direct soldering PICUS to a PCB
SOFTWARE
PICUS gives a possibility to upload software by a serial port (you do not need a Microchip programmer).
Bluetooth offers SPP, OBEX, Headset profiles.
Wi-Fi gives an access to the integrated webserver, TCP socket, embedded FTP and email clients.
We are planning to realize a visual development tool to enable using of PICUS even without any software experience.
BIRDS NEST
PICUS will have a range of "nests": boards with several kinds of sensors and with or without a display where PICUS will perform the wireless part and the CORE Cpu, all in one.
APPLICATION SCENARIO
openPICUS will be the core and the wireless part of Internet of things, sensors, wireless messaging, standard converters, home and industrial small automation and more.
The main characteristics:
HARDWARE
CPU Microchip PIC 24F 16 bit 44 pins QFN 64K Flash 8K Ram)
Wireless (Bluetooth / Wi-Fi)
Power 5V or 3,3V
Main connections: UART, Digital Inputs, Digital Outputs, Analog Inputs, PWMs, SPI display, I2C
Connector: 26 Ways IDC header (male) suitable for TH mounting or flat cable
SMT: 26 Pins for direct soldering PICUS to a PCB
SOFTWARE
PICUS gives a possibility to upload software by a serial port (you do not need a Microchip programmer).
Bluetooth offers SPP, OBEX, Headset profiles.
Wi-Fi gives an access to the integrated webserver, TCP socket, embedded FTP and email clients.
We are planning to realize a visual development tool to enable using of PICUS even without any software experience.
BIRDS NEST
PICUS will have a range of "nests": boards with several kinds of sensors and with or without a display where PICUS will perform the wireless part and the CORE Cpu, all in one.
APPLICATION SCENARIO
openPICUS will be the core and the wireless part of Internet of things, sensors, wireless messaging, standard converters, home and industrial small automation and more.
20 Cell phones with highest radiation levels
Cell phone radiation. Some consider it a heath-hazard of paramount importance. Others couldn't care less. Whichever camp you're in, there's some perverse satisfaction in clicking through CNET's countdown to see which is the most mind-melting gadget on the market.
GM Develops Augmented Reality Windshield
The entire windshield is turned into a transparent display to highlighting landmarks, obstacles and road edges on the windshield in real-time. Such a system can point out to drivers potential hazards, such as a running animal, even in foggy or dark conditions, GM says. GM uses a special type of glass coated with red-emitting and blue-emitting phosphors--a clear synthetic material that glows when it is excited by ultraviolet light. The phosphor display, created by SuperImaging, is activated by tiny, ultraviolet lasers bouncing off mirrors bundled near the windshield. Three cameras track a driver's head and eyes to determine where she is looking. [Via Technology Review]
IC Insights' capex rankings for 2010
IC Insights Inc. has raised its forecast for IC capital spending. The firm forecasts that 2010 spending will rebound and hit $40.7 billion, a 57 percent increase over 2009. This is up from its previous forecast of plus 45 percent. In 2009, capex fell 30 percent, it was noted. In 2011, IC capital spending is expected to reach $48.6 billion, up 20 percent over 2010, according to the firm. [Via EE Times]
Top 25 Chip ranking for 2009
ISuppli's final global revenue ranking for the top 25 semiconductor suppliers in 2009, in millions of U.S. dollars (click on image to enlarge). Winners: AMD, Elpida, Hynix, IBM, MediaTek, Micron and Qualcomm.Losers: Freescale, Infineon, Marvell, NEC, NXP, Panasonic, Renesas, Rohm, Sharp and Sony. The winners climbed the IC rankings in 2009. The losers fell. Still, 2009 was a tough year for all. Out of approximately 300 semiconductor suppliers measured by iSuppli Corp., two-thirds suffered falling revenues in 2009.[Via EE Times]
Firm buys Qimonda fab for $12 million
Richmond Semiconductor LLC has bought the former Qimonda fab in Sandston, Va. for $12 million, according to the Richmond Times-Dispatch.
Submit news articles/information from the web
Please limit your submissions only to the categories that are specific and relevant to this Blog! We always reserve the right to selectively publish submitted articles. You may also include your name, email and link to your home page.
Magnetic Solder to Wire 3-D Chips
A new type of solder can be melted and shaped in three dimensions under the force of a weak magnetic field. Using a magnet to pull the solder up through narrow holes makes it possible to create electrical connections between stacked silicon chips, for example. These three-dimensional chips pack more computing power in a given area, but making connections between them is expensive, a problem that the new solder might address. The solder also contains no lead, and it is stronger than other lead-free solders. {Via Technology review}
Silicon Nanophotonics to Make Your Gadgets Run Faster and Consume Less
IBM is replacing copper wiring with an avalanche of photons and electrons. They are now transmitting data streams between circuits at the nanophotonic level. Speed: 40Gbps. Power supply: Just 1.5 volts. The video in the title link explains how it works.The system is so fast and consumes so little because of electron avalanches: The receptor—called nanophotonic avalanche photodetector—catches the photon, which starts an electron chain reaction thanks to the properties of Germanium. What does this mean: Faster, smaller, and more power efficient devices. And the possibility of saying "nanophotonics" any time we want.
Infineon introduces two RF-chips for LTE and 3G
Infineon has introduced two RF-chips for LTE and 3G - SMARTi LU for highest data rates with LTE, and SMARTi UEmicro for low cost 3G devices.SMARTi LU is a highly integrated 2G/3G/LTE multi-mode RF transceiver compliant to 3GPP Rel.7 and Rel.8. It supports up to six 3G and LTE Bands simultaneously with Quad Band GSM/EDGE. Its long feature list includes LTE FDD class 4 (up to 150Mbps downlink, 50Mbps uplink) MIMO Rx diversity (2Rx + 1Tx), HSPA+, HSPA, WCDMA and GSM/GPRS/EDGE. The device is supporting the global spread of HSPA/LTE spectrum throughout a wide variety of bands. With its MIPI DigRF v4 compliant high-speed digital Baseband interface, SMARTi LU sets a milestone towards “all digital” implementation and enables the silicon intensive baseband chips to follow a faster shrink path towards smaller technology nodes such as 32nm and below. SMARTi LU is based on a standard 65nm CMOS technology provided by multiple semiconductor foundries.
The SMARTi UEmicro is a single chip 2G/3G CMOS RF transceiver for the low end segment of the 3G market. It is a cost down version of the proven and widely adopted SMARTi UE with a backward compatible hard- and software interface via DigRF v3.09. With the elimination of external Low Noise Amplifiers (LNA’s) and a simplified co-banded RF frontend without Rx filters SMARTi UEmicro is perfectly matching the mass market requirements for ultra low cost 3G handsets. SMARTi UEmicro delivers exceptional RF performance for up to three of the globally used WCDMA bands plus Dual- or Quad-Band GSM/EDGE at lowest system cost.
The SMARTi UEmicro is a single chip 2G/3G CMOS RF transceiver for the low end segment of the 3G market. It is a cost down version of the proven and widely adopted SMARTi UE with a backward compatible hard- and software interface via DigRF v3.09. With the elimination of external Low Noise Amplifiers (LNA’s) and a simplified co-banded RF frontend without Rx filters SMARTi UEmicro is perfectly matching the mass market requirements for ultra low cost 3G handsets. SMARTi UEmicro delivers exceptional RF performance for up to three of the globally used WCDMA bands plus Dual- or Quad-Band GSM/EDGE at lowest system cost.
400th Post: Microelectronics Systems News!
Starting today we will be embarking on a new series called Microelectronics Systems News!
Microelectronics Systems News, will be in the format of a Newsletter that includes items of interest in the areas of IC design, prototyping, micorelectronic systems including embedded systems and programmable system-on-chip platforms using FPGAs.
This Newsletter will be broadcast to over 4000+ existing subscribers throughout the world. There is no charge for this service.
To make a contribution, send email to Murugavel Ganesan at: murugavelganesan@gmail.com
To be added to the email notification list, subscribe using feedburner using the link in the main page.
To be deleted, follow the instructions on feedburner!
For a change of address, just add the new address and then delete the old one.
Microelectronics Systems News, will be in the format of a Newsletter that includes items of interest in the areas of IC design, prototyping, micorelectronic systems including embedded systems and programmable system-on-chip platforms using FPGAs.
This Newsletter will be broadcast to over 4000+ existing subscribers throughout the world. There is no charge for this service.
To make a contribution, send email to Murugavel Ganesan at: murugavelganesan@gmail.com
To be added to the email notification list, subscribe using feedburner using the link in the main page.
To be deleted, follow the instructions on feedburner!
For a change of address, just add the new address and then delete the old one.
LG first to use Intel's 'Moorestown' chip for smartphone
LG Electronics and Intel have announced a collaboration based on Intel's Moorestown silicon and the Linux Moblin v2.0 software platform at the Mobile World Congress in Barcelona Yesterday. The future LG device, which is being described as a smartphone is expected to be one of the first Moorestown designs to market.