ASIC
Application Specific IP

Application Specific IP

One of the major barriers for Semiconductor IP commercialization is to provide evidence for an IP's quality. A comm…

Phase-locked loops (PLLs) Demystified

Phase-locked loops (PLLs) Demystified

Over the past decade, Phase-Locked Loops (PLLs) have become an integral part of the modern ASIC design. PLLs provide th…

What Users Would Change About This Blog!

What Users Would Change About This Blog!

The best part about this survey is that you get to see what users are looking for, whats bothering them that they would…

Layoff Watch!

Layoff Watch!

Announced Worldwide Layoffs As of 30th January 2009 Infineon - 3000 Qimonda - 3000 (Bankrupt: 23 Jan 09) Renesas -…

FPGA & ASIC based design

FPGA & ASIC based design

The main diferrence between ASIC and FPGA based design is in the Back-end. In FPGAs there is not much activities in bac…

Low power design

Low power design

Primarily design for low power depends on the characteristics design being accomplished. If it is a multi-million gate …

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