Theorem proving
Formal Verification: Theorem proving
How many times in the course of a project have you heard of the term Formal Verification? This relatively short on arti…
Verification
Toyota Prius 2005: An Early Warning About Verification
In this article Richard Goering talks about a software bug in Toyota Prius 2005 and after 5 years even after a through…
Verification
Motivation: What else can we talk about verification?
Many of you already know that verification efforts are as or more important as the design efforts themselves. They cann…
Verification
Verification Sessions at DVcon 2010
Featured Tutorial: Step-By-Step Guide to Advanced Verification Tutorial!, DVcon Exhibits and Product Demos.., DVCon Pap…
Verification
Clock-Domain Crossing Verification Module
This Mentor's Verification Academy module directly addresses CDC issues by introducing a set of steps for advancing…
Modelsim
ModelSim PE Student Edition - Free HDL Simulation
Mode details about Free Simulators are here -> https://blog.digitalelectronics.co.in/2023/03/free-hdl-simulators.ht…
Verification
Questa SV/AFV: Verification Methodology Kits
Mentor Graphics provides the Methodology kit examples in open source form under the Apache-2.0 license. These kits are…
SupportNet
Questa Compatibility Matrix: Versions of Questa SV/AFV that work with different versions of other Mentor and open-source verification products
This matrix illustrates (SupportNet access needed) the version compatibility between Questa SV/AFV and different versio…
DVclub
Design Verification Club (DVclub)
DVClub is a very interesting organization. With chapters in Austin, Bangalore, Boston, Dallas, Research Triangle Park,…
Sponsored
Delivering synthesizable verification IP for testbences
Case Study:SystemVerilog VMM vs. BSV for an Ethernet MAC test bench. High-level verification languages and environment…
Toyota
Toyota's woes: More technology, more complexity
Today, cars can have as many as 70 electronic control units, or ECUs, based on microcontrollers (sometimes generically …
Latch
Are latches really bad for a design?
It is not completely correct to say that we have to avoid latches in our designs. In one of our recent projects we went…
PA semi
iPad and the A4 chip
By now you would have digested enough info about iPad from all the overflowing blogs and sites that are covering Apple…
Interview Questions
Interview Question on CPU design
A CPU has a memory unit with 32-bit instructions and a register file with 32 registers. The instruction set consists of…
Interview Questions
Interview Question
Draw the circuit diagram for barrel-shifter that can shift 3 bits in either direction. The shifter should take 3 bits a…
Tips and Tricks
Modelsim Tips & Tricks
In this article we will see how to create a simple Tcl script that tests for certain values on a signal and then adds b…
VIP
The world of HVLs and VIPs
Over the last decade functional verification of ASIC systems has witnessed a paradigm shift in verification methodologi…
Verification Plan
Verification Plan
An effective verification plan encompasses a detailed description of the complete hierachical verification methodology …
Size. Transistor Size
Single-atom transistor discovered
Researchers from Helsinki University of Technology (Finland), University of New South Wales (Australia), and University…
Verification
Dealing with clock jitter in DDR2/DDR3 based designs
For the past couple of days i have been part of a design that interfaces a DDR/DDR2 memory. But lately after a recent p…