Verification Plan

An effective verification plan encompasses a detailed description of the complete hierachical verification methodology at unit and full chip level. It is important to consider at what verification phase directed vs random tests will be applied or when to stop investing effort on building a stand alone test environment that can provide greater coverage and instead, migrate to full chip level tests that deliver a more comprehensive understanding of the sate of the chip.

A good verification plan addresses many questions like what tools can be used for stand alone and full chip and for what specific type of tests. Creation of expected result scenarios along with the self checking mechanism should be detailed to improve automation and to drive the highest return on performance. In addition to each verification phase, testbench deliverables, dependencies like RTL availability, milestones like tests to be completed or written and any assumptions need to be specified and understood thoroughly. Finally, upon completion of the verification plan it has to be reviewed by both the design and verification teams and a matrix has to be created to track test coverage and then use it to measure the completeness or progress. Is is also important to know when and how to apply technologies such as emulation and formal methods to leverage key strengths to avoid any weaknesses and achieve high design quality using the verfication effort.
Courtesy: Catherine Ahlshlager!

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  1. When you don't maintain a complete/good verification/test plan, the status of the project is left to the individual judgement of the reader of that document to interpret the raw data. Unfortunately i am seeing that happen right before my eyes and there is none to take stock of the situation.

  2. Success depends on methodical planning of tasks combined with systematic verification process. Period!


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