Reduce Power, Area and Routing Congestion
This paper , using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by …
This paper , using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by …
For both analog-to"digital converters (ADC) and digital-to"analog converters (DAC), system-level specificatio…
Product quality and reliability are first-order design requirements for any product development. This document describ…
Imagine being able to control electronics products at home and in the office, not with a direct touch but with the swee…
Since the year 2010 commercialization of the LTE technology is taking place. At the same time further enhancements of t…
The first part of this white paper explores the basic concepts behind HDMI, the markets it serves and its leadership ro…
Success in ever more competitive worldwide marketplaces demands continually smarter products and systems, which in turn…
Displays have always been a major power consumer in mobile devices. In the past, one easy way to keep power demands in …
This paper provides a summary of the features and benefits from the new IEEE-1149.7 specification commonly referred to…
The benefits of multicore are numerous, but to realize them you must avoid the common pitfalls by planning carefully an…
Systems designers are having a difficult time developing power subsystems that supply all of their system's power n…
Are we on target? Are we within budget? Are my projects contributing effectively to my operational objectives? How well…
A half-node process has been routinely used to deliver incremental improvements in process control and hardware availab…
Modern embedded and computing systems have become progressively more powerful by incorporating high-speed buses, indust…
Reverse engineering is a very common practice in semiconductor business. Companies will barely admit doing it but every…
Complying with the variety of environmental regulations has become a challenging task for electronics OEMs (Original Eq…
One of the major barriers for Semiconductor IP commercialization is to provide evidence for an IP's quality. A comm…
Instead of prolonging the painful process of finding bugs in RTL code, the design flow needs to be geared toward creati…
DRAM (Dynamic Random Access Memory) is attractive to designers because it provides a broad range of performance and is …
Android is an open source platform built by Google that includes an operating system, middleware, and applications for …
Over the past decade, Phase-Locked Loops (PLLs) have become an integral part of the modern ASIC design. PLLs provide th…
Clock domain crossing (CDC) errors in FPGAs are elusive, and locating them often requires good detective work and smart…
Most failures are not single-point; generally a single event does not entirely account for the failure. Often multiple …
This book is intended for those who work in or provide components for industries that use digital signal processing (DS…
"Debugging" is the most valuable engineering skills, not taught in any formal setting, and often learned the …
Many embedded system-on-a-chip (SoC) designs make use of multiple processors, but do so in an application-specific or &…
Hardware design data and design flows present unique requirements that are not met by software configuration management…
According to Mitch Weaver, corporate vice president for front-end verification at Cadence, the e verification language…
Broadcom recently announced a single-chip HSUPA baseband processor that integrates key 3G mobile technologies and will…
How many times in the course of a project have you heard of the term Formal Verification? This relatively short on arti…
In this article Richard Goering talks about a software bug in Toyota Prius 2005 and after 5 years even after a through…
Many of you already know that verification efforts are as or more important as the design efforts themselves. They cann…
Featured Tutorial: Step-By-Step Guide to Advanced Verification Tutorial!, DVcon Exhibits and Product Demos.., DVCon Pap…
This Mentor's Verification Academy module directly addresses CDC issues by introducing a set of steps for advancing…
Mode details about Free Simulators are here -> https://blog.digitalelectronics.co.in/2023/03/free-hdl-simulators.ht…
Mentor Graphics provides the Methodology kit examples in open source form under the Apache-2.0 license. These kits are…
This matrix illustrates (SupportNet access needed) the version compatibility between Questa SV/AFV and different versio…
DVClub is a very interesting organization. With chapters in Austin, Bangalore, Boston, Dallas, Research Triangle Park,…
Case Study:SystemVerilog VMM vs. BSV for an Ethernet MAC test bench. High-level verification languages and environment…
Today, cars can have as many as 70 electronic control units, or ECUs, based on microcontrollers (sometimes generically …
It is not completely correct to say that we have to avoid latches in our designs. In one of our recent projects we went…
By now you would have digested enough info about iPad from all the overflowing blogs and sites that are covering Apple…
A CPU has a memory unit with 32-bit instructions and a register file with 32 registers. The instruction set consists of…
Draw the circuit diagram for barrel-shifter that can shift 3 bits in either direction. The shifter should take 3 bits a…
In this article we will see how to create a simple Tcl script that tests for certain values on a signal and then adds b…
Over the last decade functional verification of ASIC systems has witnessed a paradigm shift in verification methodologi…
An effective verification plan encompasses a detailed description of the complete hierachical verification methodology …
Researchers from Helsinki University of Technology (Finland), University of New South Wales (Australia), and University…
For the past couple of days i have been part of a design that interfaces a DDR/DDR2 memory. But lately after a recent p…