Infrastructure Needs for Multi-Voltage Designs


Before we start looking at implementing a Multi-Voltage design there are certain questions that need to be answered to find out from process/library perspective such as

  1. Available Operating Voltages (PVT)
  2. Do we have special cells such as Level Shifters/Isolation cells/Power Gating Switches?
  3. If Level Shifter exists, what kinds of level shifters are available? (Ex: Enable Level Shifter etc)
  4. What are the different corners that need to be used for sign-off?
  5. How should we handle OCV?
  6. How accurate are these timing models? Is NLDM good enough or do we need CCS/ECSM models?
  7. Do we have special cells with Dual Rails(ex: Retention Flops)? If yes How is the timing captured for each rails?
  8. Are these cells characterized for Power, do they have State Dependent Path Dependent Information?
  9. If special cells exist, is it modeled according to EDA tools requirement?
  10. For Feed through implementation, do we have special Always On Buffers? What's the impact of routing the secondary power pins of these buffers on routing resources?
  11. Given range of Operating Voltages, is there an easy way at early stage of implementation cycle to judge on right Voltage selection? (power/performance product)
  12. Am I getting required power savings by implementing the design in Multi-Voltage style? For ex. If number of special cells required to implement this are too many, is it worth the effort? Can we look at an alternate way of saving power?

Multi Voltage magic


In the last few weeks i have been quite busy with a lot of research on low power design. There are so many tutorials on Low Power and everyone's concerns/questions seems to be dancing around Multi-Voltage design. What I could sense was there were lot of designers Implementing Multi-Supply(Power-Gating) as opposed to real Multi-Voltage design. There are 3 classics style of new design style i found

  1. Multi-Supply(Power Gating)
  2. Static Multi-Voltage
  3. Dynamic Voltage and Frequency Scaling

Lets us discuss about Multi-Voltage design in the forthcoming posts. Like any other design implementation, MV design has its own challenges and much more difficult to sign-off.

I would like to classify the different stages of the design into small segments so that we can discuss one by one.

  • Design Infrastructure
  • Architectural level consideration
  • Microarchitecture
  • RTL Design
  • RTL functional verification
  • Implementation
  • Functional Sign-Off
  • Silicon Signoff
  • Resources For Help

Next post is going to be a in-depth technical article i guess!

Vt Cells and Spacing Requirements


Multi-Vt placement/spacing concerns

I was just thinking about most common concerns faced today in addressing leakage power. Multi-Vt spacing requirement is something everyone faces as multi-vt has become more or less part of regular implementation flow, thought of sharing the same today.

What's Multi-Vt?

In trying to meet the stringent leakage requirements, usage of Multi-Vt cells has become more or less must have. Let me give a small description of the same.

Balancing timing and leakage power requires the use of multiple libraries whose cells operate at different threshold voltages. Cells, which operate at higher threshold voltage are slower and less leaky, where as cells that operate at lower threshold voltage are faster and very leaky. Optimization engines meet timing goals by using the low-Vth cells on critical timing paths and high-Vth cells on non-critical paths. The low- and high-Vth cells have the same footprint for equivalent functions. Depending upon where you perform optimization in the flow, these cells are either just swapped (ECO) or paths are resynthesized (Synthesis/Placement) to meet timing/leakage goals.

Is it so simple?

Even though the above sound simple, it comes with its own implications that need to be addressed during chip finishing stage to meet certain process requirements.

Maintaining the same footprint requires careful library design because the low-Vth cells have a different well implant to create their lower threshold voltage. If this implant extended to the edges of the cell, it could overlap the edge of an adjacent high-Vth cell. The cells are therefore designed with a small buffer space around the edges, Low Vt and High Vt cells can be placed side by side. Figure 1/2 below demonstrates a simple scenario of Vt spacing requirements

Problems can occur if cells of the same Vth type are placed with a small space between them and a filler cell of the opposite Vth type is used to fill the gap. This mismatched filler creates a gap in the implant regions that violates design rules. Typically this problem is addressed by inserting filler cells intelligently.

How should I handle it?

Most of the current generation P&R tools like ICC/Astro will insert suitable filler cells next to the VT cells, when needed. Typically, filler cells are used to fill any spaces between regular library cells to avoid planarity problems and provide electrical continuity for power and ground. Because the High Vt cells have a different diffusion layer over them, a High Vt filler cell needs to be placed between High Vt cells, and a Low Vt filler cell needs to be placed between Low Vt cells.