Multi-Vt cells are standard cells built in several threshold-voltage flavours (for example low, standard and high Vt) with the same footprint, so a tool can swap a fast, leaky cell for a slower, low-leakage one without moving anything. The catch is that each Vt flavour is defined by its own implant or Vt-setting layer, and those layers have minimum width, spacing and area rules. When cells of different Vt types sit next to each other, or a narrow gap is filled with the wrong filler, the layout can break those rules. Handling Vt spacing is therefore a library, placement and filler-insertion problem, not just a timing one.
I was thinking about the most common concerns we face today in addressing leakage power. The multi-Vt spacing requirement is something everyone meets, because multi-Vt has become more or less part of the regular implementation flow, so I thought of sharing it.
Key takeaways
- Low-Vt cells are fast and leaky; high-Vt cells are slower and leak far less. Optimisation uses low-Vt only where timing needs it.
- Equivalent cells in every Vt flavour share one footprint, so swaps during ECO do not disturb placement or routing.
- Each Vt flavour is drawn on its own layer, and that layer has minimum width, spacing and area design rules.
- Violations usually come from narrow slivers: a single thin cell, or a small gap filled with the wrong filler, between cells of another Vt type.
- Vt-aware placement legalisation plus Vt-matched filler insertion prevents most violations; physical verification (DRC) is the final check.
What is multi-Vt?
To meet stringent leakage requirements, multi-Vt cells have become more or less a must-have. Balancing timing and leakage power requires multiple libraries whose cells operate at different threshold voltages. Cells that operate at a higher threshold voltage are slower and less leaky, whereas cells that operate at a lower threshold voltage are faster and much leakier. Optimisation engines meet timing goals by using low-Vt cells on critical timing paths and high-Vt cells on non-critical paths.
The low-Vt and high-Vt cells have the same footprint for equivalent functions. Depending on where you optimise in the flow, cells are either simply swapped (ECO) or paths are resynthesised (synthesis or placement) to meet timing and leakage goals.
Why leakage changes so much with Vt
Below threshold, drain current falls exponentially as Vt rises. The rate is set by the subthreshold swing, often quoted in the range of roughly 70 to 100 mV per decade for bulk planar devices and closer to the ideal 60 mV per decade at room temperature for well-controlled FinFETs. A useful rule of thumb follows from that.
| Vt step (illustrative) | Subthreshold swing (illustrative) | Approximate leakage ratio |
|---|---|---|
| 50 mV | 80 mV/decade | about 4x |
| 100 mV | 80 mV/decade | about 18x |
| 100 mV | 100 mV/decade | about 10x |
The ratio is 10 raised to (Vt step divided by swing). The numbers above are illustrative only; real ratios come from your library's leakage tables at the relevant corner, and the ratio between flavours grows sharply at high temperature, which is why leakage sign-off is usually done at the hot corner.
Common Vt flavours
| Flavour | Speed | Leakage | Typical use |
|---|---|---|---|
| ULVT / LVT | Fastest | Highest | Critical paths, clock-critical logic, high-frequency cores |
| SVT (RVT) | Medium | Medium | Bulk of the logic in many performance designs |
| HVT / UHVT | Slowest | Lowest | Non-critical paths, always-on and standby logic |
The names and the number of flavours vary by foundry and node. Many advanced libraries also offer the same function in different channel lengths, which behaves like an extra Vt knob and brings its own layer rules.
Is it so simple?
Even though the above sounds simple, it comes with its own implications that have to be addressed at the chip-finishing stage to meet process requirements.
Keeping the same footprint requires careful library design, because each Vt flavour is created with a different implant or Vt-setting layer. If that layer extended right to the edge of a cell, it could overlap the edge of an adjacent cell of a different Vt type. Cells are therefore designed with a small buffer space around their edges, so that low-Vt and high-Vt cells can be placed side by side legally. The library documentation (or the technology file) lists which abutments are legal and which need extra space.
Where the violations come from
Problems occur when cells of the same Vt type are placed with a small space between them and a filler cell of the opposite Vt type is used to fill the gap. The mismatched filler creates a break or a sliver in the implant region that violates the design rules. Typical patterns are:
- Sliver between two same-Vt cells: two HVT cells with a one-site gap, filled by an LVT filler, leaving a narrow LVT region narrower than the minimum implant width.
- Isolated narrow cell: a single, very narrow LVT cell (an inverter, say) dropped into a row of HVT cells. The LVT region it creates can be below minimum width or minimum area.
- Notches and jogs: implant edges that step back and forth from row to row can create notches smaller than the minimum spacing.
- Row ends and boundaries: mismatched end-cap or boundary cells at macro edges and power-domain edges.
Worked example (illustrative numbers)
Assume a library with a placement site width of 0.1 um and a rule that any Vt implant region must be at least 0.4 um wide. Two HVT cells are placed with a gap of two sites (0.2 um). If the filler step drops an LVT filler into that gap, the LVT region is 0.2 um wide, half the minimum, so DRC reports a minimum-width violation. Filling the gap with an HVT filler merges the region with its neighbours and the violation disappears. The same rule also means that an LVT cell narrower than four sites cannot stand alone among HVT cells unless the library builds the required margin into the cell itself, or the placer keeps a legal neighbour beside it. Real values depend on the foundry rule deck.
How should I handle it?
Most current-generation place-and-route tools (Synopsys IC Compiler II and Fusion Compiler, Cadence Innovus, and older tools such as ICC and Astro when this post was first written) can insert suitable filler cells next to the Vt cells when needed. Filler cells fill any spaces between regular library cells to keep the wells and implant layers continuous and to provide electrical continuity for the power and ground rails. Because high-Vt cells have a different implant layer over them, a high-Vt filler should be placed between high-Vt cells, and a low-Vt filler between low-Vt cells.
A practical flow looks like this:
- Read the rules early. Collect the Vt layer width, spacing and area rules, and the legal abutment table, from the library and foundry documents before floorplanning.
- Use Vt-aware placement. Enable the placer's implant or Vt spacing rules so that legalisation avoids illegal slivers, rather than finding them at the end.
- Limit Vt mixing in tight areas. Very dense regions with frequent Vt swaps generate the most violations. Some teams cap the low-Vt percentage, or bias swaps towards groups of cells rather than isolated ones.
- Insert Vt-matched fillers. Run filler insertion with the filler list ordered so the tool picks a filler whose Vt matches its neighbours, and with decap fillers handled the same way.
- Re-check after every ECO. Late timing ECOs that swap Vt or resize cells are the most common source of new violations. Remove and re-insert fillers around changed cells, then rerun DRC.
- Sign off with DRC. The foundry rule deck in the physical verification tool is the final authority; the P&R checks are an early filter.
Common mistakes
- Treating Vt swaps as free because the footprint matches, and leaving implant checks to final DRC.
- Using a generic filler list that ignores Vt, so the tool fills gaps with whichever filler fits first.
- Forgetting that decap cells, tap cells and end-caps also carry a Vt layer.
- Running a late leakage-recovery ECO (mass swap to HVT) without re-running filler insertion and DRC.
- Judging leakage savings at the typical corner, when the hot corner is where leakage and the Vt ratio matter most.
FAQ
Why do low-Vt and high-Vt cells share the same footprint?
So that optimisation can swap one for the other in place. If the footprint changed, every swap would need re-legalisation and possibly rerouting, which would make leakage recovery after routing impractical.
Does multi-Vt still matter in FinFET and gate-all-around nodes?
Yes. The way the threshold is set can differ (work-function metals, implants, or a mix, depending on the process), but libraries still come in several Vt flavours, and each flavour still has layer rules that constrain how cells of different types can abut.
What is the role of filler cells here?
Fillers close the gaps between placed cells so that wells, implant layers and power rails are continuous. Choosing a filler with the same Vt as its neighbours avoids creating illegal implant slivers.
Who owns these rules, the library team or the implementation team?
Both. The library team builds margins into each cell and publishes the legal abutments. The implementation team must enable the matching placement rules, use the right filler list and re-check after every ECO.
Your comments will be moderated before it appears here.