Vt Cells and Spacing Requirements

Multi-Vt placement/spacing concerns

I was just thinking about most common concerns faced today in addressing leakage power. Multi-Vt spacing requirement is something everyone faces as multi-vt has become more or less part of regular implementation flow, thought of sharing the same today.

What's Multi-Vt?

In trying to meet the stringent leakage requirements, usage of Multi-Vt cells has become more or less must have. Let me give a small description of the same.

Balancing timing and leakage power requires the use of multiple libraries whose cells operate at different threshold voltages. Cells, which operate at higher threshold voltage are slower and less leaky, where as cells that operate at lower threshold voltage are faster and very leaky. Optimization engines meet timing goals by using the low-Vth cells on critical timing paths and high-Vth cells on non-critical paths. The low- and high-Vth cells have the same footprint for equivalent functions. Depending upon where you perform optimization in the flow, these cells are either just swapped (ECO) or paths are resynthesized (Synthesis/Placement) to meet timing/leakage goals.

Is it so simple?

Even though the above sound simple, it comes with its own implications that need to be addressed during chip finishing stage to meet certain process requirements.

Maintaining the same footprint requires careful library design because the low-Vth cells have a different well implant to create their lower threshold voltage. If this implant extended to the edges of the cell, it could overlap the edge of an adjacent high-Vth cell. The cells are therefore designed with a small buffer space around the edges, Low Vt and High Vt cells can be placed side by side. Figure 1/2 below demonstrates a simple scenario of Vt spacing requirements

Problems can occur if cells of the same Vth type are placed with a small space between them and a filler cell of the opposite Vth type is used to fill the gap. This mismatched filler creates a gap in the implant regions that violates design rules. Typically this problem is addressed by inserting filler cells intelligently.

How should I handle it?

Most of the current generation P&R tools like ICC/Astro will insert suitable filler cells next to the VT cells, when needed. Typically, filler cells are used to fill any spaces between regular library cells to avoid planarity problems and provide electrical continuity for power and ground. Because the High Vt cells have a different diffusion layer over them, a High Vt filler cell needs to be placed between High Vt cells, and a Low Vt filler cell needs to be placed between Low Vt cells.