Advanced Microcontroller Bus Architecture (AMBA):
The AMBA™ on-chip interconnect system is an established open specification that details a strategy on the interconnection and management of functional blocks that makes up a System-on-Chip (SoC). It is a high-speed, high-bandwidth bus that supports multi-master bus management to maximize system performance. AHB serves the need for high-performance SoC as well as aligning with current synthesis design flows. It facilitates "first-time-correct" development of systems with one or more high performance preipherals, DMA controllers, on-chip memory and other interfaces. As increasing numbers of companies adopting the AMBA system, it has rapidly emerged as the de-facto standard for SoC interconnection and IP library development. AMBA enhances a reusable design methodology by defining a common backbone for SoC modules.
The AMBA specification defines the protocol used to move data across an AMBA interconnect architecture without defining the architecture itself. This provides the system designer with the flexibility to create architectures ranging from a simple 'point-to-point' connection through to complex, high performance architectures. AHB-Lite, a subset of AHB enables further simplification and increased performance for interconnect with only a single master while the Multi-layer AHB architecture allows the system designer to dramatically increase the capacity, and hence performance, of the architecture.
Some of the features..
- Single active rising edge clock.
- High-performance operation maximized by the ability to use the full clock cycle.
- Aligns with synthesis design flows .
- Multiple bus masters Optimizes system performance by sharing resources between different bus masters such as the main processor, DMA controllers or secondary processors.
- Pipelined and burst transfers, allows high speed memory and peripheral access without the requirement for additional cycles on the bus.
- Burst transfers allow optimal use of memory interfaces by giving advance information of the nature of the transfers.
- Split transactions are supported.
- Maximize the use of the system bus bandwidth by enabling high latency slaves to release the system bus during the dead time while the slave is completing its transaction.
- Wide data bus configuration (32/64/128 up to 1024-bit wide).
- Support for high-bandwidth data-intensive application using wide on-chip memory.