Showing posts with label Nor. Show all posts
Showing posts with label Nor. Show all posts

Flash Memories - Types

Although all flash memories use the same basic storage cell, there are a number of ways in which the cells can be interconnected within the overall memory array. The two most prominent architectures are known as NOR and NAND; these terms, derived from traditional combinatorial logic, indicate the topology of the array and the manner in which individual cells are accessed for reading and writing. Initially, there was a basic distinction between these two fundamentally different architectures, with NOR devices exhibiting inherently faster read times and NAND devices offering higher storage densities (because the NAND cell is about 40% smaller than the NOR cell). NOR Flash memories are considered to be the best choice for densities up to 256 Mbits, while NAND types are preferred for 512-Mbits and up. This is the best compromise between large data storage capacities and cell size - and consequently, final die size.

NOR Flash Memory:
NOR-type Flash memories are based on technologies that evolved largely from the first non-volatile memory technologies. They are typically organized as a number of blocks between 16 Kbytes and 128 Kbytes, each of which can be individually erased or programmed. The architecture can be either uniform if all of the blocks are the same size or asymmetrical when the blocks vary in size. The array can be organized as a single piece of memory or split into dual or multiple banks, and in some cases, one block (called boot block) located at the top or the bottom of the address space, is dedicated to the storage of the boot code. NOR Flash memories usually have a random access for reading at byte/word level and sometimes a page access mode, allowing the reader to view an entire page of 2 to 4 words in one go. When very rapid read operations are required, the Flash memory is equipped with a burst read mode, which allows data to be transferred on every clock cycle.

Parallel and Serial Interface:
Parallel Access and Serial Access Parallel buses were primarily used to interface flash memories with microcontrollers and microprocessors through an address bus, a data bus and a control bus. By default, the term "Flash memory" refers to a parallel interface memory. The data bus can be organized as x8 bits, x16 bits or x32 bits. In some cases, address and data buses can be multiplexed. They are available in densities of up to 128 Mbits. Because of their rapid read times, Flash memories are traditionally used for basic code or code-plus-parameter storage where greater flexibility compared to EPROM is more important than the additional unit cost. More recently, they have pervaded many new applications where their key functions are to store both code and data. This was achieved by dual operations supported by dual or multiple bank architecture, which enable programming/erasing operations in one bank while reading from another bank. The serial bus is used to connect a Flash memory to a microcontroller or an ASIC equipped with a serial bus. Serial buses are input/output interfaces supporting a mixed address/data protocol. The serial bus connectivity reduces the number of interface signals required. For example, the SPI bus, the most popular serial bus for serial Flash memories, requires only 4 signals (data in, data out, clock and chip select) compared to 21 signals necessary to interface a 10-bit address parallel memory. As a result, the number of pins of the memory package (memory and bus master) is reduced, as is the number of PCB tracks. Consequently, a serial memory can fit into a smaller and less expensive package. However, serial Flash memories are available in lower densities than Flash memories. The communication throughput between serial Flash memory and master processor is lower than for traditional Flash memories. Consequently, the time to download code into the serial memory and execute it from the memory is longer. As a result, serial Flash memories are usually used for small code storage associated with a cache RAM. This is called a code shadowing architecture. The executable code is first programmed in the memory and it is write protected. After power-up, it is downloaded from memory to RAM from where it is executed by the master processor.

NAND or NOR design

NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate.

Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND ( the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance pmos's are in series connection which again increases the resistance).