Showing posts with label TAU 2008. Show all posts
Showing posts with label TAU 2008. Show all posts

TAU 2008

ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU Workshop) will be held at The Portola Plaza Hotel at Monterey Bay in Monterey, California on February 25-26, 2008. The workshop is co-sponsored by IEEE/CAS and ACM/SIGDA.

The TAU series of workshops provide an informal forum for practitioners and researchers working on temporal aspects of digital systems to disseminate early work and engage in a free discussion of ideas.

The fifteenth in the TAU series, the TAU 2008 workshop invites submissions from all areas related to the timing properties of digital electronic systems, including but not limited to:

Formal theories and methods
System-level timing
Transistor-level timing
Circuit-level timing
Sensitivity analysis
Full custom design analysis
Integrated functional-temporal analysis
Incremental analysis
Timing issues in low power design
Power-delay trade-offs
Adjacent line switching and coupling
Delay models and metrics
Layout impact on timing
Timing-driven layout optimization
Timing-driven synthesis and re-synthesis
Circuit optimization
Uncertainty-based analysis
Incorporation of RETs in timing
Reliability impact on performance
Process & environmental variation models
Statistical analysis technique
Clocking, synchronization, and skew
Clock domains, static/dynamic logic
Novel clocking schemes
Special circuit families
Asynchronous systems