"Latch" Vs "Flip Flop"

A flip-flop is Edge sensitive: Output only changes on rising (or falling) edge of clock.
A latch is Level sensitive: Output changes whenever clock/Enable is high (or low)

A common implementation of a flip-flop is a pair of latches (Master/Slave flop).

Latches are sometimes called “transparent latches”, because they are transparent (input directly connected to output) when the clock is high.

The clock to a latch is primarily called the “enable”.

For more information have a look at the picture below.

Deprecated Hardware:

Latches:

1. Use flops, not latches
2.  Latch-based designs are susceptible to timing problems
3. The transparent phase of a latch can let a signal “leak” through a latch — causing the signal to affect the output one clock cycle too early
4. It’s possible for a latch-based circuit to simulate correctly, but not work in real hardware, because the timing delays on the real hardware don’t match those predicted in synthesis

Flip-flops:

1. Limit yourself to D-type flip-flops
2. Some FPGA and ASIC cell libraries include only D-type flip flops. Others, such as Altera’s APEX FPGAs, can be configured as D, T, JK, or SR flip-flops.

• For every signal in your design, know whether it should be a flip-flop or combinational. Examine the log file e.g. dc shell.log to see if the flip-flops in your circuit match your expectations, and to check that you don’t have any latches in your design.
• Do not assign a signal to itself (e.g. a <= a; is bad). If the signal is a flop, use an enable to cause the signal to hold its value. If the signal is combinational, then assigning a signal to itself will cause combinational loops, which are very bad.

If you are looking for code snippets for the following types of hardware, please leave a comment.

1. Flops with Waits and Ifs
2. Flops with Synchronous Reset
3. Flops with Chip-Enable
4. Flops with Chip-Enable and Mux on Input
5. Flops with Chip-Enable, Mux's, and Reset

Glitches, Hazards and Lizards

A glitch is a momentary error condition on the output of a circuit due to unequal path delays in a circuit. It is seen as an additional pulse or pulses on the output. Between a time the input signals are settled and the output signals are being established a glitch can occur if there is an hazard(functional or logical).

Glitches due to functional errors can occur when two input signals or more change in values at the same time. It is related to the function that is being implemented and cannot be removed by adding extra circuit.

Glitches due to logical hazard can occur only when one i/p signal changes it value. A logic hazard can be removed by add extra circuit. A logic hazard can be static or dynamic.

Low power design

Primarily design for low power depends on the characteristics design being accomplished. If it is a multi-million gate design we cannot implement any technique that is gate specific, it has to be a global technique.

1. Multi-Vdd, variable Vdd and Multi-Vth seems to be a good global solution.
2. Reducing the clock speed will result in low power consumption, but on the cost of performance.
3. Using power headers and power footer transistors on logic gates cuts down power.
4. You could separate the design in blocks, which can go in to sleep mode.
5. Another solutions is variable VDD and variable frequency (as Intel or AMD do).This means, you adapt VDD and frequency to the necessary performance.
6. Gated clocks and Logic Addressable clocks, dis adv - timing problems due to improper latching of signals, and difficult to test.
7. -ve edge triggered flops, (nor+inv) = 1.5 gates, +ve edge triggered flops, (and+inv) = 2.5 gates, so -ve has less gates, less glitching and hence low power.

Any more thoughts and ideas are welcome.

Verilog Awareness - Interview Questions

Q: Given the following Verilog code, what value of "a" is "displayed"?

always @(clk)
begin
a = 0;
a <= 1; $display(a); end

Q: Given the following snippet of Verilog code, draw out the waveforms for "clk" and "a".

always @(clk)
begin
a = 0;
#5 a = 1;
end

Q: What is the difference between the following two lines of Verilog code?

#5 a = b;
a = #5 b;

Q: Write Verilog to provide a divide-by-3 clock from the standard clock.

Q: What is the difference between:

c = foo ? a : b;

and

if (foo) c = a; else c = b;

Q: Using the given, draw the waveforms for the following (each version is separate, i.e. not in the same run):

reg clk;
reg a;
always #10 clk = ~clk;

(1) always @(clk) a = # 5 clk;
(2) always @(clk) a = #10 clk;
(3) always @(clk) a = #15 clk;

Now, change to a wire, and draw for:

(4) assign #5 a = clk;
(5) assign #10 a = clk;
(6) assign #15 a = clk;

Glue Logic

glue logic is the circuitry needed to achieve compatible interfaces between two (or more) different off-the-shelf integrated circuits.

An example of glue logic is the address decoder which with older processors like the 6502 or Z80 had to be added externally to divide up the addressing space of the processor into RAM, ROM and I/O. Newer versions of the same processors (such as the WDC 65816 or Zilog eZ80) instead have internal address decoders so glueless interfacing to the most common external devices becomes possible.

Sometimes, glue logic is used to encrypt the proprietary electronics circuitry by the vendor and to prevent the product from being illegally counterfeited.

Application Specific Integrated Circuit ( ASIC )

An application-specific integrated circuit or ASIC comprises an integrated circuit (IC) with functionality customized for a particular use (equipment or project), rather than serving for general-purpose use.

For example, a chip designed solely to run a cash register is an ASIC. In contrast, a microprocessor is not application-specific, because users can adapt it to many purposes.

The initial ASICs used gate-array technology.

The British firm Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customisation occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customised by both metal and polysilicon layers. Some base dies include RAM elements.

In the late 1980s, the availability of logic synthesis tools (such as Design Compiler) that could accept hardware description language descriptions using Verilog and VHDL and compile a high-level description into to an optimised gate level netlist brought "standard-cell" design into the fore-front. A standard-cell library consists of pre-characterized collections of gates (such as 2 input nor, 2 input nand, invertors, etc.) that the silicon compiler uses to translate the original source into a gate level netlist. This netlist is fed into a place and route tool to create a physical layout. Routing applications then place the pre-characterized cells in a matrix fashion, and then route the connections through the matrix. The final output of the "place & route" process comprises a data-base representing the various layers and polygons in GDS-II format that represent the different mask-layers of the actual chip.

Finally, designers can also take the "full-custom" route in implementing an ASIC. In this case, an individual description of each transistor occurs in building the circuit. A "full-custom" implementation may function five times faster than a "standard-cell" implementation. The "standard-cell" implementation can usually be implemented quite a bit quicker and with less risk of errors, than the "full-custom" choice.

As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) has increased from 5000 gates to 20 million or more. Modern ASICs often include 32-bit processors and other large building-blocks. Many people refer to such an ASIC as a SoC - System on a Chip.

The use of intellectual property (IP) in ASICs has become a growing trend. Many ASIC houses have had standard cell libraries for years. However IP takes the reuse of designs to a new level. Designers of most complex digital ICs now utilise computer languages that describe electronics rather than code. Many organizations now sell tested functional blocks written in these languages. For example, one can purchase CPUs, ethernet or telephone interfaces.

For smaller designs and/or lower production volumes, ASICs have started to become a less attractive solution, as field-programmable gate arrays (FPGAs) grow larger, faster and more capable. Some SoCs consist of a microprocessor, various types of memory and a large FPGA.

So having said, this blog is dedicated to Digital Electronics, VLSI, ASICs, SOCs etc.