FIFO Depth Calculation: Formula and 9 Worked Scenarios

Check out the FIFO Depth Calculator here: https://blog.digitalelectronics.co.in/p/fifo-depth-calculator.html

FIFO depth is the number of entries a buffer needs so that a burst from a fast or bursty writer never overflows while a slower or less frequent reader drains it. The basic method is simple: work out how long the write burst lasts, count how many items the reader can remove in that same time, and the difference is the minimum depth. On top of that you add margin for read latency and, in an asynchronous FIFO, for the pointer synchronisation delay.

A First-In-First-Out (FIFO) depth calculation is a crucial part of designing FIFO buffers or queuing elements in digital systems. The depth determines how much data has to be buffered, which depends on the rate at which data is written and the rate at which it is read. This post gives the general formula, then works through nine classic scenarios that appear in design reviews and interviews.

Key takeaways

• Minimum depth = burst size minus the items read during the burst: D = B − (B / write rate) × read rate.
• Use effective rates. A writer that sends one item every two clocks runs at half its clock frequency; a reader with three idle cycles between reads runs at a quarter of its clock.
• If the reader is at least as fast as the writer, the depth only has to cover latency and synchronisation, not the burst.
• Always assume the worst case: the reader starts as late as allowed and the writer packs its data as tightly as the specification permits.
• An asynchronous FIFO needs extra entries for the two or three clock cycles it takes a Gray-coded pointer to cross between clock domains.
• FIFO depth only covers a finite burst. If the long-term write rate is higher than the long-term read rate, no depth is enough.

The general formula

Define the following terms:

• Fx = frequency of the writing side.
• Fy = frequency of the reading side.
• B = data burst (number of items written back to back).

Then:

• Burst duration = B / Fx.
• Data received during the burst, Rx = (B / Fx) × Fy, assuming the reader reads for the whole burst.
• Extra storage needed at the FULL condition, Backlog = B − Rx = B × (Fx − Fy) / Fx.
• To accommodate a latency or response time T in the receiver, add another T × Fx locations.
• The receiver also needs time to read the backlog, so the idle time between bursts must be long enough. This minimum time is called the mop-up time: backlog / Fy = B × (Fx − Fy) / (Fx × Fy).

When the writer or reader has idle cycles, replace Fx and Fy with effective rates. A side that transfers one item and then waits I idle cycles transfers one item every (I + 1) clocks, so its effective rate is F / (I + 1). With the effective rates Wx and Wy, the minimum depth is:

D = B − (B / Wx) × Wy, rounded up to a whole entry

A short worked example

Take a burst of B = 10 items written at F1 = 30 MHz with no idle cycles, and a reader clocked at F2 = 40 MHz with 10 idle cycles between two reads. The reader therefore removes one item every 11 read clocks, an effective rate of 40 / 11 = 3.64 million items per second.

• Burst duration = 10 / 30 MHz = 333.3 ns.
• Items read in that time = 333.3 ns × 3.64 per microsecond = 1.21, so one complete read.
• Depth = 10 − 1.21 = 8.79, rounded up to 9 entries.

In a synchronous design, 9 is enough. In an asynchronous design you would add margin for the pointer synchronisers (see below), and a power-of-two depth such as 16 is the usual choice when the pointers are Gray coded.

Worked scenarios

Let us consider the following scenarios. In each one, block X writes into the FIFO and block Y reads from it, and the burst length is the number of data items to be transferred.

Scenario 1: Fx > Fy, no idle cycles

The specification is Fx = 80 MHz (writing frequency), Fy = 50 MHz (reading frequency) and a burst length of 120 items. With no idle cycles, data is written and read on consecutive clock cycles.

• Time to write one item = 1 / 80 MHz = 12.5 ns, so the whole burst takes 120 × 12.5 ns = 1500 ns.
• Time to read one item = 1 / 50 MHz = 20 ns, so block Y reads 1500 ns / 20 ns = 75 items during the burst.
• The remaining 120 − 75 = 45 items must be held by the FIFO.

So the minimum FIFO depth is 45.

Scenario 2: Fx > Fy, one clock cycle delay between successive writes and reads

Same frequencies and burst length as Scenario 1. This is a tricky way of asking the question: "one clock cycle delay between two successive writes" means each write happens one clock after the previous one, which is exactly the no-idle case. The answer is the same as Scenario 1, a depth of 45. In an interview, say out loud how you are reading the wording before you calculate.

Scenario 3: Fx > Fy, one idle cycle between writes, three idle cycles between reads

Fx = 80 MHz, Fy = 50 MHz, burst of 120 items, one idle clock cycle after each write and three idle clock cycles after each read.

• Block X takes two clock cycles per item: 2 × (1 / 80 MHz) = 25 ns. The burst therefore takes 120 × 25 ns = 3000 ns.
• Block Y takes four clock cycles per item: 4 × (1 / 50 MHz) = 80 ns. In 3000 ns it reads 3000 / 80 = 37.5, so 37 whole items.
• The remaining 120 − 37 = 83 items must be held by the FIFO.

So the minimum FIFO depth is 83.

Note: if the question gives duty cycles instead of idle cycles, the method is the same. Here the write enable has a 50% duty cycle (1 in 2) and the read enable a 25% duty cycle (1 in 4).

Scenario 4: Fx < Fy, no idle cycles

Fx = 30 MHz, Fy = 50 MHz, burst of 120 items, no idle cycles. The reader is faster than the writer, so data never accumulates and a FIFO depth of one is sufficient in principle. If the two clocks are asynchronous, the FIFO still needs a few entries to cover the synchronisation delay of the write pointer into the read domain.

Scenario 5: Fx < Fy, one idle cycle between writes, three idle cycles between reads

Fx = 30 MHz, Fy = 50 MHz, burst of 120 items, one idle cycle per write and three per read. The read clock is faster, but the reader idles more, so its effective rate is lower than the writer's.

• Write time per item = 2 × (1 / 30 MHz) = 66.67 ns; the burst takes 120 × 66.67 ns = 8000 ns.
• Read time per item = 4 × (1 / 50 MHz) = 80 ns; in 8000 ns the reader removes 8000 / 80 = 100 items.
• The remaining 120 − 100 = 20 items must be held by the FIFO.

So the minimum FIFO depth is 20. This scenario is a good test: candidates who only compare clock frequencies conclude that no buffering is needed.

Scenario 6: Fx = Fy, no idle cycles

Fx = Fy = 30 MHz, burst of 120 items, no idle cycles. If the two clocks are the same clock with no phase difference, no FIFO is needed at all. If there is a phase difference, a FIFO depth of 1 will be sufficient. If the clocks only have the same nominal frequency but come from different sources, they will drift relative to each other, and the FIFO must cover the synchroniser latency and the drift (this is the elastic buffer case in serial links).

Scenario 7: Fx = Fy, one idle cycle between writes, three idle cycles between reads

Fx = Fy = 50 MHz, burst of 120 items, one idle cycle per write and three per read.

• Write time per item = 2 × (1 / 50 MHz) = 40 ns; the burst takes 120 × 40 ns = 4800 ns.
• Read time per item = 4 × (1 / 50 MHz) = 80 ns; in 4800 ns the reader removes 4800 / 80 = 60 items.
• The remaining 120 − 60 = 60 items must be held by the FIFO.

So the minimum FIFO depth is 60.

Scenario 8: rates given as data per clock cycles

The writer sends 80 data items in every 100 clock cycles, and the position of those 80 items within the 100 cycles is random (they may arrive in any 80 of the 100 cycles). The reader takes 8 data items in every 10 clock cycles. The burst size is 160. Both sides use the same clock.

Worst case: the 80 items of one window are written in its last 80 cycles and the 80 items of the next window in its first 80 cycles. That puts all 160 items into 160 consecutive clock cycles.

• In 160 clock cycles the reader removes 160 × 8 / 10 = 128 items.
• The remaining 160 − 128 = 32 items must be held by the FIFO.

So the minimum FIFO depth is 32. The key step is spotting the back-to-back worst case across the window boundary.

Scenario 9: rates given as clock ratios and enable duty cycles

The write clock (X) runs at one quarter of the read clock (Y). The period of the read enable en_y is 100 times the period of the write enable en_x, which means a burst of 100 items is written in each en_y period. The read enable en_y has a 25% duty cycle. What depth avoids overflow and underflow?

• Assume the read clock is 100 MHz, so the write clock is 100 MHz / 4 = 25 MHz.
• Write time per item = 1 / 25 MHz = 40 ns; a burst of 100 items takes 100 × 40 ns = 4000 ns.
• With a 25% duty cycle, en_y is active for only 1000 ns of each 4000 ns period.
• Worst case, nothing is read for the other 3000 ns, and the data written in that time must be held by the FIFO: 3000 ns / 40 ns = 75 items.

So the minimum FIFO depth is 75. During the 1000 ns read window the reader, at 100 MHz, can remove up to 100 items, which is enough to empty the 75 stored items plus the 25 written during the window.

Summary of the scenarios

Scenario	Write side	Read side	Burst	Minimum depth
1	80 MHz, no idle	50 MHz, no idle	120	45
2	80 MHz, write every clock	50 MHz, read every clock	120	45
3	80 MHz, 1 idle	50 MHz, 3 idle	120	83
4	30 MHz, no idle	50 MHz, no idle	120	1 (plus sync margin)
5	30 MHz, 1 idle	50 MHz, 3 idle	120	20
6	30 MHz, no idle	30 MHz, no idle	120	0 or 1
7	50 MHz, 1 idle	50 MHz, 3 idle	120	60
8	80 in 100 clocks	8 in 10 clocks	160	32
9	25 MHz	100 MHz, 25% enable	100	75

Checking the numbers with a simulation

A hand calculation treats reads as a smooth rate. Real reads happen on clock edges, so the true peak occupancy can differ by one entry depending on where the edges fall. The small Verilog model below runs a write clock and a read clock, writes one item every WGAP write clocks, reads one item every RGAP read clocks when data is available, and reports the largest occupancy seen.

`timescale 1ns/10ps
// Behavioural occupancy model: how many entries does a burst leave behind?
module fifo_occ_tb;
  parameter real TW = 12.5;   // write clock period, ns (80 MHz)
  parameter real TR = 20.0;   // read clock period, ns (50 MHz)
  parameter integer WGAP  = 2; // write once every WGAP write clocks
  parameter integer RGAP  = 4; // read once every RGAP read clocks
  parameter integer BURST = 120;

  reg wclk = 0, rclk = 0;
  always #(TW/2) wclk = ~wclk;
  always #(TR/2) rclk = ~rclk;

  integer written = 0, read = 0, wcnt = 0, rcnt = 0, occ, max_occ = 0;

  always @(posedge wclk) begin
    if (written < BURST && wcnt % WGAP == 0) written = written + 1;
    wcnt = wcnt + 1;
  end

  always @(posedge rclk) begin
    if (read < written && rcnt % RGAP == 0) read = read + 1;
    rcnt = rcnt + 1;
  end

  always @(written or read) begin
    occ = written - read;
    if (occ > max_occ) max_occ = occ;
  end

  initial begin
    #20000;
    $display("TW=%0.1f TR=%0.1f WGAP=%0d RGAP=%0d BURST=%0d max occupancy=%0d",
             TW, TR, WGAP, RGAP, BURST, max_occ);
    $finish;
  end
endmodule

Compiled and run with Icarus Verilog 12.0, it reports a peak occupancy of 45 for Scenario 1, 82 for Scenario 3, 21 for Scenario 5 and 60 for Scenario 7. Scenario 3 comes out one below the hand figure because the hand method rounds the reads down; Scenario 5 comes out one above because the first read lands slightly later than the smooth-rate assumption. The lesson is to treat the hand result as a minimum and add an entry or two of margin, then let the simulation or a formal check confirm the final number. Change the parameters on the command line, for example iverilog -Pfifo_occ_tb.WGAP=2 -Pfifo_occ_tb.RGAP=4 fifo_occ.v.

Extra depth for asynchronous FIFOs

When the write and read clocks are unrelated, the FIFO compares a write pointer and a read pointer that live in different clock domains. Each pointer is converted to Gray code and passed through a two-flop (or three-flop) synchroniser into the other domain. Clifford Cummings' SNUG 2002 paper, "Simulation and Synthesis Techniques for Asynchronous FIFO Design", is the standard reference for this structure.

• The full flag in the write domain sees the read pointer two or three write clocks late, so the FIFO looks fuller than it is. The writer may stall a little early, which is safe but costs effective depth.
• The empty flag in the read domain sees the write pointer late, so the first read after a burst starts a few read clocks late. That delay is the latency T in the general formula, and it adds roughly T × Fx entries.
• Gray-coded binary pointers work most simply with a power-of-two depth, so the calculated minimum is usually rounded up to the next power of two. Non-power-of-two depths are possible but need a different pointer scheme.

Common mistakes

• Comparing clock frequencies instead of effective data rates (Scenario 5 is the trap).
• Assuming the reader starts at the same instant as the writer when the specification allows it to start later.
• Forgetting the worst-case packing of data across window boundaries (Scenario 8).
• Ignoring synchroniser latency and flag pessimism in an asynchronous FIFO.
• Sizing for one burst without checking the mop-up time. If the next burst can arrive before the backlog drains, the bursts add up and the depth must be recalculated for the combined burst.
• Applying the formula when the long-term write rate exceeds the long-term read rate. In that case the FIFO will eventually overflow whatever its depth, and the design needs flow control (backpressure) instead.

Note: for bursts of data that are written for a partial amount of time over a given number of cycles, and read either continuously or also for a partial amount of time, the calculation has to account for the next burst as well.

How interviewers probe FIFO depth

• They change one word in the question, such as "delay" versus "idle cycles" (Scenario 2), to see whether you read the specification carefully.
• They ask what happens if the clocks are asynchronous, expecting Gray-coded pointers, synchronisers and extra margin.
• They ask for the minimum idle time between bursts, which is the mop-up time.
• They ask how you would verify the depth, expecting a simulation with worst-case traffic, assertions on overflow and underflow, and coverage of the full condition.

FIFO depth calculator

Enter the write and read clock frequencies, the burst length and any idle cycles to estimate the depth.

Enter the following parameters and click on the Calculate button to get the minimum FIFO depth.

Parameter	Value	Unit
Writing frequency (Fx)		MHz
Reading frequency (Fy)		MHz
Burst length (B)		Number of data items
Idle clock cycles of sender (ix)		Number of clock cycles
Idle clock cycles of receiver (iy)		Number of clock cycles

Result
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FAQ

Why round the depth up rather than to the nearest whole number?

A FIFO cannot hold a fraction of an entry. Rounding down by even one entry means the last item of a worst-case burst is lost, so always round up.

Do I always need a power-of-two depth?

No. A synchronous FIFO can have any depth. Asynchronous FIFOs with Gray-coded pointers are simplest at a power of two, which is why they are usually built that way.

What if the reader is faster than the writer?

Then data does not accumulate during the burst, and the depth only needs to cover read latency and pointer synchronisation, typically a handful of entries.

Where can I try my own numbers?

Use the FIFO Depth Calculator on this blog, then confirm the result with a cycle-level simulation like the one above.