VHDL Interview Question(s)

1. What are the two key concepts in the simulation semantics of VHDL and how does each concept help VHDL simulation produce waveforms that match the behaviour that we expect?
2. What is the advantage of RTL simulation in comparison to simulation as defined by the VHDL standard?
3. What is the disadvantage of RTL simulation in comparison to simulation as defined by the VHDL standard?
4. For each of the architectures muruku 1. . . muruku 4, answer the following questions.
• INSTRUCTIONS:
1. Is the code legal VHDL?
2. If the code is legal VHDL:
• Answer whether the behaviour of the signal z has the same behaviour as in the main architecture of sumit.
• Answer whether the code is synthesizable.
• If the code is synthesizable, answer whether it adheres to good coding practices.

If the the code is not legal, not synthesizable, or does not follow good coding practices, explain why.

entity sumit is
port (
a, b, clk : in std_logic;
z : out std_logic
);
end sumit;

architecture main of sumit is
signal m : std_logic;
begin
process ( clk )
begin
if rising_edge( clk ) then
m <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= not m; end if; end process; end main;

1. Muruku 1
• architecture muruku_1 of sumit is
  signal m : std_logic;
  begin
  process ( clk )
  begin
  if rising_edge( clk ) then
  m <= a or b; z <= not m; end if; end process; end muruku_1;
2. Muruku_X
• architecture muruku_X of sumit is
  signal m, p : std_logic;
  begin
  process ( clk )
  begin
  if rising_edge( clk ) then
  m <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= p; end if; end process; p <= not m; end muruku_X;
3. Muruku_2
• architecture muruku_2 of sumit is
  signal m, p : std_logic;
  begin
  if (a or b) = ’1’ generate
  m <= ’1’; end generate; if (a or b) = ’0’ generate m <= ’0’; end generate; process ( clk ) begin if rising_edge( clk ) then p <= m; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= not p; end if; end process; end muruku_2;
4. Muruku_3
• architecture muruku_3 of sumit is
  begin
  process
  begin
  wait until rising_edge(clk);
  wait until rising_edge(clk);
  z <= not (a or b); end process; end muruku_3;
5. Muruku_4
• architecture muruku_4 of sumit is
  signal m, p : std_logic;
  begin
  process ( clk )
  begin
  if rising_edge( clk ) then
  m <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then p <= m; end if; end process; z <= not p; end muruku_4;

Difficulty: Medium