RTL Synthesis is done by matching high level code against templates or patterns. It is important to use idioms that your synthesis tool recognizes. If you aren’t careful, you could write code that has the same behavior as one of the idioms, but which results in inefficient or incorrect hardware.
Most synthesis tools agree on a large set of idioms, and will reliably generate hardware for these idioms. This post is based on the idioms that Synopsys, Xilinx, Altera, and Mentor Graphics are all able to synthesize. We consider combinational loops to be unsynthesizable. Although it is obviously possible to build a circuit with a combinational loop, in most cases the behaviour of such a circuit is undefined.
Initial Values
Initial values on signals (UNSYNTHESIZABLE)
signal bad_signal : std_logic := ’0’;Reason: In most implementation technologies, when a circuit powers up, the values on signals are completely random. Some FPGAs are an exception to this. For some FPGAs, when a chip is powered up, all flip flops will be ’0’. For other FPGAs, the initial values can be programmed.
Wait For
Wait for length of time (UNSYNTHESIZABLE)
wait for 10 ns;Reason: Delays through circuits are dependent upon both the circuit and its operating environment, particularly supply voltage and temperature.
Different Wait Conditions
wait statements with different conditions in a process (UNSYNTHESIZABLE)
-- different clock signals
process
begin
wait until rising_edge(clk1);
x <= a;
wait until rising_edge(clk2);
x <= a;
end process;
-- different clock edges
process
begin
wait until rising_edge(clk);
x <= a;
wait until falling_edge(clk);
x <= a;
end process;
Reason: Processes with multiple wait statements are turned into finite state machines. The wait statements denote transitions between states. The target signals in the process are outputs of flip flops. Using different wait conditions would require the flip flops to use different clock signals at different times. Multiple clock signals for a single flip flop would be difficult to synthesize, inefficient to build, and fragile to operate.
Multiple “if rising edge”s in Same Process
Multiple if rising edge statements in a process (UNSYNTHESIZABLE)
process (clk)Reason: The idioms for synthesis tools generally expect just a single if rising edge statement in each process. The simpler the VHDL code is, the easier it is to synthesize hardware. Programmers of synthesis tools make idiomatic restrictions to make their jobs simpler.
begin
if rising_edge(clk) then
q0 <= d0;
end if;
if rising_edge(clk) then
q1 <= d1;
end if;
end process;
“if rising edge” and “wait” in Same Process
An if rising edge statement and a wait statement in the same process (UNSYNTHESIZABLE)
process (clk)Reason: The idioms for synthesis tools generally expect just a single type of flop-generating statement
begin
if rising_edge(clk) then
q0 <= d0;
end if;
wait until rising_edge(clk);
q0 <= d1;
end process;
in each process.
“if rising edge” with “else” Clause
The if statement has a rising edge condition and an else clause (UNSYNTHESIZABLE).
process (clk)Reason: Generally, an if-then-else statement synthesizes to a multiplexer. The condition that is tested in the if-then-else becomes the select signal for the multiplexer. In an if rising edge with else, the select signal would need to detect a rising edge on clk, which isn’t feasible to synthesize.
begin
if rising_edge(clk) then
q0 <= d0;
else
q0 <= d1;
end if;
end process;
“if rising edge” Inside a “for” Loop
An if rising edge statement in a for-loop (UNSYNTHESIZABLE-Synopsys)
process (clk) beginReason: just an idiom of the synthesis tool.
for i in 0 to 7 loop
if rising_edge(clk) then
q(i) <= d;
end if;
end loop;
end process;
Some loop statements are synthesizable. For-loops in general are described in the VHDL cookbook by Ashenden. For the curious reader, the above code is an 8-bit serial-to-parallel converter. The signal d is the serial data and q is the parallel data. On each clock cycle, d is copied into one of the bits of q.
For the synthesizable alternatives, please discuss/leave comments below.
