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VHDL Books There are dozens of great books talking about VHDL modeling, simulation and synthesis. Here are some of them: (1) VHDL Made Easy by Pellerin & Taylor (2) Digital Design System Design with VHDL by Mark Zwolinski (3) Introductory VHDL from Simulation to Synthesis by Yalamanchili (4) VHDL Coding and Logic Synthesis with Synopsys by Weng Fook Lee (5) Digital Design and Modeling with VHDL and Synthesis by K. C. Chang (6) …
RTL Synthesis is done by matching high level code against templates or patterns. It is important to use idioms that your synthesis tool recognizes. If you aren’t careful, you could write code that has the same behavior as one of the idioms, but which results in inefficient or incorrect hardware. Most synthesis tools agree on a large set of idioms, and will reliably generate hardware for these idioms. This post is based on the idioms that Sy…
1. **For a combinational process in VHDL, the sensitivity list should contain all of the signals that are read in the process. Please give a detailed reason and an exception to this statement.** *Reason:* The sensitivity list in a combinational process specifies the signals that, when changed, should trigger the execution of the process. In VHDL, a combinational process should be sensitive to all the signals that are read within the process t…
This article provides a comprehensive methodology that highlights the best practices for mixed-language design integration and automatically comes up with an option for designers to select the optimal method for integration. There are broadly five ways of making mixed-language connections. Pros and cons of each of these approaches and their comparison is described in terms of the usage scenarios, performance implications of using one versus t…
Verilog started out as a proprietary simulator in 1984 and enjoyed considerable success due to its C like syntax. In 1990, Cadence Design Systems made the language public. It became an IEEE standard in 1995. VHDL was developed under contract to the U.S. Department of Defense. It became an IEEE standard in 1987. VHDL has its roots in Ada. For many years there was intense competition between Verilog and VHDL for mind share and market share. Both l…
Hints Avoid more package references than needed Keep all objects and subprograms in the nearest possible scope Keep local objects invisible outside a package Transfer stable component declarations into components packages Re-use functionality of standard packages as much as possible Size of VHDL Units should be reasonable for synthesis A VHDL unit should not exceed 500 lines of code A process or subprogram should not exceed 100 lines of code Com…
To Avoid common Warnings Store each VHDL unit into a separate file except package header and body Signal assignments for renaming purposes should be avoided The names of clocks and resets should be unique in the whole design Soft macros: Data types at ports: std_(u)logic(_vector) Avoid custom data types (e.g., multidimensional arrays, records, enumeration types) Avoid gated clocks unless absolutely necessary Avoid latches unless absolutely neces…
Critical Policies to Keep note! Balance clock to delta accuracy Pull-ups and pull-downs have to be modeled on chip level Communication between modules using text-IO is forbidden No characters with a lower rank than space may occur in text-IO Testbench and DUT should be compiled into the same library Asynchronous parts should be placed into separate entities VHDL units should take into account later floorplanning A FSM must be described in a sepa…
To Avoid common Errors A configuration declaration is needed for each architecture in the design Design-internal references must use library work Use selected names in binding indications and ’use’ clauses only Configuration must be in a separated file except the latest level of hierarchy All primary unit names must be unique in the project library Identifier casing should be uniform in all VHDL code Length of entity names should not exceed 32 c…
Portability Language for modeling should be VHDL-87 VHDL-93 keywords should not be used Verilog keywords should not be used SDF keywords should not be used IKOS keywords should not be used Allowable replacement characters are forbidden Tool specific types may not be used Configuration declarations must have the configuration name and the entity name in one line Never redefine standard operators, subprograms, attributes, and packages Design-inte…
When Compiling (VHDL): A configuration declaration is needed for each architecture in the design Design-internal references must use library work Use selected names in binding indications and ’use’ clauses only Testbench and DUT should be compiled into the same library Avoid more package references than needed Partitioning VHDL Code VHDL units should take into account later floorplanning Asynchronous parts should be placed into separate entities…
Coding of circuit behavior and architecture is one of the most critical steps in the whole chip development project. It has a major impact on logic synthesis, routing results, timing robustness, verifiability and testability. The HDL Coding Guidelines help chip and macro developers/teams to rapidly understand each other's code. Macro based designs integrate easier if these common coding styles are followed. This also applies to externally de…
What are the two key concepts in the simulation semantics of VHDL and how does each concept help VHDL simulation produce waveforms that match the behaviour that we expect? What is the advantage of RTL simulation in comparison to simulation as defined by the VHDL standard? What is the disadvantage of RTL simulation in comparison to simulation as defined by the VHDL standard? For each of the architectures muruku 1. . . muruku 4, answer the foll…
VHDL Disadvantages VHDL is verbose, complicated and confusing Many different ways of saying the same thing Constructs that have similar purpose have very different syntax (case vs. select) Constructs that have similar syntax have very different semantics (variables vs signals) Hardware that is synthesized is not always obvious (when is a signal a flip-flop vs latch vs combinational) VHDL Advantages VHDL supports unsynthesizable constructs that …