SystemC AMS – A New Proposal For Mixed-Signal Verification

With increasing analog and mixed-signal content on systems-on-chip, design teams are looking for faster ways to run system-level simulations. They also need to incorporate mixed-signal functionality into system-level design and architectural exploration. Spice and Fast Spice are too slow for full-chip, top-level verification, and even languages like Verilog-AMS can pose a performance bottleneck. In this article by Richard Goering, he speaks about what SystemC AMS is about, refrerring to white papers on Linear signal flow (LSF), Electrical linear networks (ELN) and Timed data flow (TDF).

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