Silicon class testing, usually just called "class test", is the final electrical test a chip goes through after it has been packaged. The name comes from Intel, whose manufacturing flow runs wafer fabrication, sort (wafer-level test), assembly, burn-in and then class, where each packaged part is tested and classified by how fast it runs and how much power it draws. Elsewhere in the industry the same step is simply called final test, package test or FT. Its job is to make sure only good parts ship and that each one is sold in the right speed and power grade.
Image courtesy: Intel Corporation.
Key takeaways
- Class test is Intel's name for final test: it runs on packaged units, after wafer sort, assembly and (for many products) burn-in.
- It checks that the finished product works and meets its data sheet: function, maximum frequency, power, voltage margins and I/O behaviour.
- It is also where parts are binned, so one design can ship as several products with different clock speeds and power ratings.
- Catching a defect here costs far less than a field return, but more than catching it at sort, which is why the two test steps share the work.
Where class test sits in the flow
Silicon class testing is one of several test steps between a finished wafer and a shipped product. Each step screens for a different kind of failure.
| Step | What is tested | Main purpose |
|---|---|---|
| In-line and e-test (parametric) | Test structures in the wafer scribe lines: transistors, resistors, contact chains | Check the process itself is in control |
| Sort (wafer probe) | Every die on the wafer, through a probe card | Mark failing die so they are not packaged |
| Assembly | Not a test step: good die are cut, mounted and packaged | Build the product |
| Burn-in | Packaged units stressed at high voltage and temperature | Push weak, early-life failures to fail before shipping |
| Class (final test) | Each packaged unit on automatic test equipment (ATE) and a handler | Confirm the product meets spec, and grade it |
| System-level test (on some products) | The part running real software on a board | Catch faults that structural tests miss |
This is a useful correction to a common description. Class test is not where individual transistors, logic gates or memory cells are characterised one by one. Device-level behaviour is checked much earlier on scribe-line test structures, and the logic and memory inside the chip are exercised as a whole through scan, built-in self-test (BIST) and functional patterns. What class test verifies is the complete, packaged product.
What class testing checks
The objective is to verify the functionality and performance of the finished chip. A typical class test program covers:
- Continuity and opens/shorts: are all package pins connected, and is nothing shorted after assembly?
- DC parametrics: leakage and standby current, input and output levels, supply current.
- Structural tests: scan (ATPG) patterns for stuck-at and delay faults, and memory BIST for the on-chip arrays.
- Functional and speed tests: patterns run at speed across a range of frequencies and voltages to find the maximum frequency (Fmax) and minimum operating voltage (Vmin).
- Power: active and idle power dissipation, measured against the limits for each product grade.
- I/O and analogue: high-speed interface loopback, PLL lock, temperature sensor and fuse checks.
Power dissipation and maximum frequency are the two results that matter most commercially, because they decide which product a part becomes.
Why class testing matters
Silicon class testing is an important step because it is the last chance to catch a bad part before it reaches a customer. Some defects only appear after packaging: cracked die, bond or bump failures, or faults that show only at speed and temperature. Testing the packaged part, often at more than one temperature, closes that gap.
It also protects margin. A part that runs reliably at a higher clock or lower power can be sold as a higher-value product, while one that misses the top grade can still ship in a lower grade instead of being scrapped.
The economics follow the familiar "rule of ten" used in test engineering: the cost of finding a defect rises by roughly an order of magnitude at each later stage, from wafer to package to board to system to the field. That rule is a rule of thumb, not a precise law, but it explains why test is split between sort and class instead of being done all at once.
Worked example: binning at class
The numbers below are illustrative only. Suppose 10,000 packaged units of one processor design reach class test, and the product has three speed grades.
| Result at class | Units | Share |
|---|---|---|
| Passes at 4.0 GHz within the power limit (top grade) | 3,800 | 38% |
| Passes at 3.6 GHz (middle grade) | 4,100 | 41% |
| Passes at 3.2 GHz (entry grade) | 1,400 | 14% |
| Fails (functional, leakage or power) | 700 | 7% |
The class yield here is 93%, and the split between grades drives revenue as much as the yield does. If a process improvement moves 10% of units from the middle to the top grade, the product line earns more without a single extra wafer being made. This is why class test data is fed back to the fab and the design team, not just used for pass or fail.
Common misunderstandings
- "Class test is a development activity." It is a production step run on every unit shipped. During development, the same test program is debugged and correlated on early silicon, but in volume it is a manufacturing operation.
- "Sort already tested everything." Sort cannot see assembly defects, and probe cards limit how fast and how hot the die can be tested. Class covers what sort cannot.
- "Silicon class" means a class of silicon. The word "class" refers to classifying parts into grades, not to a type of material.
- Treating test time as free. Every second on an ATE costs money across millions of units, so test engineers trim and reorder tests to keep coverage high and time low.
FAQ
Is class test the same as final test?
Yes, in practice. "Class" is Intel's term; most other companies and test houses call it final test (FT) or package test.
What is the difference between sort and class?
Sort tests each die while it is still on the wafer, using a probe card. Class tests the packaged part in a socket on a handler, usually at controlled temperature, and assigns it to a speed and power grade.
Does every chip go through burn-in before class?
No. Burn-in is expensive, so many products use reduced or sampled burn-in, or replace it with voltage stress during test, once the process is mature.
What happens to parts that fail class?
Depending on the failure, they may be downgraded to a lower grade, sent for failure analysis to find the root cause, or scrapped.
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