How Do You Decide on a Clock Network? Trees, H-Trees, Meshes and More

You decide on a clock network by starting from the chip's timing, power and variation budgets, then picking the cheapest distribution structure that meets them. A plain buffered clock tree, built by clock tree synthesis, suits most ASIC blocks. Balanced H-trees, fishbone (spine) structures and tree-driven meshes are used when skew, on-chip variation or very high frequency make a simple tree too risky, at the cost of more wire and power.

This post explains what a clock network is, the factors that drive the choice, the main topologies and how to compare them with numbers.

Key takeaways

• The clock network decides how much of the clock period is left for logic, through skew and jitter, and it is one of the largest single consumers of dynamic power on a chip.
• Trees are cheapest in wire and power; meshes give the lowest skew and best tolerance of variation but burn the most power; H-trees and fishbone structures sit between them.
• Most real chips are hybrids: a balanced global structure feeding local trees, sometimes with a mesh in high-performance regions.
• Source synchronous clocking is an interface technique between chips or blocks, not an on-chip distribution topology.
• Choose by budget: write down the skew, jitter and power targets first, then test each candidate against them.

What a clock network is

A clock network is the system of wires and buffers that distributes the clock signal from its source, usually a PLL, to all the synchronous elements in a chip, such as flip-flops, latches, registers and memories. It is one of the most critical parts of a chip design, because it affects performance, power consumption and reliability at the same time. Every flip-flop sees the clock, and the clock toggles every cycle, so any weakness in the network shows up everywhere.

The factors that influence the design of a clock network

• Clock frequency: the higher the frequency, the harder it is to distribute the clock with low skew and jitter and to meet the chip's timing constraints, because skew and jitter become a larger fraction of a shorter period.
• Clock skew: the difference in arrival time of the clock at different flip-flops. Skew eats into setup margin on some paths and hold margin on others, and can cause timing violations and functional errors, so it must be controlled. Not all skew is bad: tools can use deliberate "useful skew" to borrow time between stages.
• Clock jitter: the variation in the period or phase of the clock from cycle to cycle, caused mainly by the PLL and by supply noise on the clock buffers. Jitter reduces timing margin, so it should be kept low through good PLL design, quiet supplies and fewer, stronger buffer stages.
• Power consumption: clock power depends on the number and size of buffers, the length and width of wires, the clock pin capacitance of the flip-flops and the switching activity. The clock toggles every cycle, so its activity is the highest on the chip and clock power is often a large fraction of total dynamic power. It should be optimised, mainly through clock gating and by avoiding excess wire.
• Reliability and variation: buffers and wires must be robust against process, voltage and temperature variation, and against ageing and electromigration. Variation turns into unplanned skew, which STA models as on-chip variation (OCV) derates. A network with a long uncommon path between launch and capture flops pays more OCV penalty. This affects yield and lifetime.
• Area and routing resources: clock nets often use wider, shielded routing on upper metal layers (non-default rules), which takes tracks from signal routing.

The main clock topologies

Tree (hierarchical buffered tree)

A tree uses multiple levels of buffers to distribute the clock from a single source to the sinks. Clock tree synthesis (CTS) tools build it automatically, balancing delay to each sink. It achieves lower power and area than a mesh, but it is more exposed to skew and jitter from unequal path lengths, buffer delay differences and variation, because each sink has its own long uncommon path from the root.

H-tree

An H-tree is a balanced, symmetric tree. The clock goes to the centre of the chip, then splits into two branches that end at the centres of the two halves, then again into quadrants, and so on in the shape of repeated letter H. Every endpoint is the same wire distance from the source, so nominal skew is very low. Its weaknesses are that real sinks are not evenly spread, so local trees still have to absorb the difference, that it is sensitive to process variation because it has no redundant paths, and that it can use more wire than a simple tree for uneven designs. It uses much less wire and power than a full mesh.

H-tree

Mesh (grid)

A mesh uses a grid of wires driven from many points, often by a tree or H-tree above it, with cross-links that short neighbouring branches together. Because nearby sinks are electrically tied, local differences average out, giving lower skew and better tolerance of variation than a tree. The cost is more power and area from the redundant wire and the large drivers needed to switch it. Tree-driven meshes have long been used in high-performance microprocessors.

Mesh Network

Fishbone (spine)

A fishbone uses a central trunk, or spine, driven strongly from one or a few points, with perpendicular ribs that carry the clock to local trees across the block. Tapping points on the ribs are chosen to balance load and delay for each region. It uses less wire and power than an H-tree or mesh spread over the same area, and is simple to route in row-based layouts. It has more skew along the spine and ribs than an H-tree, so it suits moderate frequencies or is combined with local balancing.

Hybrid and multi-source structures

Most large chips combine these. A typical approach is a balanced H-tree or spine to a set of tap points, then conventional trees, or a local mesh, from each tap. EDA tools support this as multi-source clock tree synthesis. It captures most of the skew benefit of a mesh at a power closer to a tree.

Source synchronous clocking

Source synchronous clocking is used between chips or between distant blocks, rather than for distribution inside one block. The transmitter sends a forwarded clock or strobe together with a group of data signals, for example one strobe per byte lane in DDR memory interfaces, and the receiver samples the data with that clock. Because clock and data travel through matched paths, the skew between them is greatly reduced, which removes the need for a tightly balanced global clock between the two ends. The costs are extra pins, sensitivity to mismatch between the clock and data paths, duty cycle distortion and the need for a clock domain crossing at the receiver.

Source Synchronous

Comparing the topologies

Topology	Skew	Variation tolerance	Power and wire	Typical use
Buffered tree (CTS)	Moderate	Lower	Lowest	Most ASIC blocks, low and mid frequency
H-tree	Low (nominal)	Moderate	Moderate	Global distribution to balanced tap points
Fishbone (spine)	Moderate	Moderate	Low to moderate	Row-based blocks, moderate frequency
Mesh (grid)	Lowest	Highest	Highest	High-performance processor cores
Hybrid / multi-source	Low	High	Moderate	Large high-speed SoCs
Source synchronous	Low between clock and data	Depends on path matching	Extra pins and I/O	Chip-to-chip and memory interfaces

These are relative ratings that hold for typical designs, not fixed rules.

Worked example: what skew and jitter cost

The numbers in this example are illustrative. Take a 1 GHz clock, a period of 1,000 ps, with a flip-flop clock-to-output delay of 60 ps, setup time of 40 ps and 30 ps of jitter allowance.

• With a buffered tree giving 50 ps of skew, the logic budget is 1,000 - 60 - 40 - 30 - 50 = 820 ps.
• With a tree-driven mesh giving 15 ps of skew, it is 1,000 - 60 - 40 - 30 - 15 = 855 ps, about 4% more time for logic.

Now the power side, again illustrative. Dynamic clock power is roughly C x V² x f, since the clock switches every cycle. If the tree presents 1 nF of total clock capacitance at 0.8 V and 1 GHz, clock power is about 1e-9 x 0.64 x 1e9 = 0.64 W. If a mesh adds 40% more capacitance, that becomes about 0.9 W. Clock gating that stops half the sinks for half the time saves roughly a quarter of the sink-side capacitance switched.

The decision is then whether 35 ps of extra logic time is worth about a quarter of a watt. For a processor core chasing frequency it often is. For an IoT controller at 200 MHz, where 50 ps is 1% of a 5,000 ps period, it clearly is not.

Steps to decide on a clock network

1. Clock specification: define the clock requirements: target frequencies, number of clock domains, skew and jitter budgets, power budget, number and spread of sinks, and reliability targets. Include the PLL jitter specification.
2. Choose the topology: using the trade-offs above, choose a global structure (tree, H-tree, spine, mesh or hybrid) and the local structure under it. Estimate skew and power for each candidate with early floorplan data.
3. Clock synthesis: generate the network with CTS tools or custom methods, with skew targets, maximum transition and capacitance limits, non-default routing rules and the chosen clock gating structure.
4. Clock optimisation: refine with buffer insertion and sizing, wire sizing and routing, shielding, useful skew and clock gating, reducing skew, jitter, power and area while meeting timing. Keep launch and capture flops of critical paths on common branches as long as possible, so that common path pessimism removal (CRPR) recovers more margin.
5. Sign-off: verify with STA across corners and OCV, check clock power, electromigration and supply noise on clock buffers, and confirm the clock duty cycle at the sinks.

The design of a clock network is a complex, iterative process that needs careful analysis and optimisation. A good clock network improves the performance, power efficiency and reliability of a chip.

Choosing a topology: rules of thumb

• If power and area are critical and the frequency is moderate, use a conventional buffered tree with aggressive clock gating, or a fishbone in row-based blocks.
• If skew and timing closure are critical across a large die, use an H-tree or spine to balanced tap points with local trees, or multi-source CTS.
• If on-chip variation and very high frequency dominate, use a tree-driven mesh in the critical regions and accept the power cost.
• Between chips or for wide memory interfaces, use source synchronous clocking with matched clock and data paths.

Examples from published work

A 10 nm system-on-chip product used a flexible full-chip clock network topology with a synthesis algorithm based on a hybrid metaheuristic search. Compared with a conventional ASIC methodology, the authors reported on average 16.98% better global skew, 42.75% less divergence on critical clock paths and a 64.5% shorter clock balancing phase (Teh et al., IEEE Access, 2021).

A clock balancing methodology for large and complex ASIC designs, presented at an IEEE seminar in Dallas, used custom clock tree synthesis that considers process variation and minimises the non-common part of the clock tree between launch and capture flops. This reduces timing uncertainty and improves timing closure.

A source synchronous design note from Microsemi for SmartFusion2 SoC FPGA devices uses dedicated DDR I/Os to send data and clock between chips, and describes the timing constraints and analysis needed for correct operation.

Common mistakes

• Chasing zero skew everywhere, which wastes power; hold fixing and useful skew often matter more.
• Forgetting that skew affects hold as well as setup; low skew trees can still have hold violations on short paths.
• Placing clock gating cells too close to the root, or too close to the sinks, so either power saving or balancing suffers.
• Ignoring supply noise on clock buffers, which shows up as jitter in silicon but not in nominal STA.
• Calling a source synchronous interface a clock topology for on-chip distribution.

FAQ

What is the difference between a clock tree and a clock mesh?

A tree gives each sink one path from the source; a mesh ties many paths together in a grid. The mesh averages out differences, giving lower skew and better variation tolerance, but uses more wire and power.

Is an H-tree the same as a clock tree?

An H-tree is a particular, geometrically balanced kind of tree. CTS tools build general trees balanced by buffer delay, which fit uneven sink placement better.

How much power does a clock network use?

It depends on the design, but because the clock switches every cycle and reaches every flip-flop, it is commonly one of the largest single parts of dynamic power. Clock gating is the main way to reduce it.

Does source synchronous clocking remove skew?

It greatly reduces skew between the forwarded clock and its data, because they travel through matched paths. Mismatch in the board, package or I/O still leaves some skew that must be budgeted.

References

• E. K. Teh, M. Zawawi, M. F. P. Mohamed and N. A. Mat Isa, Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique, IEEE Access, 2021: https://ieeexplore.ieee.org/document/9328752
• Clock Distribution and Balancing Methodology For Large and Complex ASIC Designs, IEEE CAS Society Dallas chapter seminar: https://ewh.ieee.org/soc/cas/dallas/documents/clock_balance_ieee_seminar04.pdf
• Microsemi (now part of Microchip), Source Synchronous Clock Designs: Timing Constraints and Analysis, application note AC373 (SmartFusion2 and IGLOO2)