How do you decide on a clock network?

A clock network is a system of wires and buffers that distributes the clock signal to all the synchronous elements in a chip, such as flip-flops and registers. The clock network is one of the most critical components of a chip design, as it affects the performance, power consumption, and reliability of the chip.

The factors that influence the design of a clock network:

• The clock frequency: The higher the clock frequency, the more challenging it is to distribute the clock signal with low skew and jitter, and to meet the timing constraints of the chip.
• The clock skew: The clock skew is the difference in arrival time of the clock signal at different points in the chip. Clock skew can cause timing violations and functional errors, so it should be minimized as much as possible.
• The clock jitter: The clock jitter is the variation in the period or phase of the clock signal due to noise or interference. Clock jitter can degrade the signal quality and reduce the timing margin of the chip, so it should be reduced as much as possible.
• The power consumption: The power consumption of the clock network depends on the number and size of the buffers, the length and width of the wires, and the switching activity of the clock signal. The power consumption of the clock network can be a significant fraction of the total power consumption of the chip, so it should be optimized as much as possible.
• The reliability: The reliability of the clock network depends on the robustness of the buffers and wires against process variations, temperature variations, voltage fluctuations, and aging effects. The reliability of the clock network can affect the yield and lifetime of the chip, so it should be enhanced as much as possible.

Steps to decide on a clock network:

• Clock specification: The first step is to define the clock requirements for the chip, such as the target frequency, skew, jitter, power, and reliability.
• Clock synthesis: The next step is to generate a preliminary clock network topology that meets the clock requirements, using automated tools or manual methods. The clock network topology can be hierarchical or mesh-based, depending on the trade-offs between performance, power, and complexity.
• Clock optimization: The final step is to refine and improve the clock network topology using various techniques, such as buffer insertion, buffer sizing, wire sizing, wire routing, wire shielding, and clock gating. The goal is to minimize the skew, jitter, power consumption, and area of the clock network while meeting the timing constraints of the chip.

The design of a clock network in a chip is a complex and iterative process that requires careful analysis and optimization. A good clock network can improve the performance, power efficiency, and reliability of a chip.

To choose a clock topology, one should consider the various trade-offs discussed above and select the one that best suits the design requirements and constraints. 

For example, if power consumption and area overhead are critical, then source synchronous topology may be preferred. If clock skew and timing closure are critical, then H-tree or fishbone topology may be preferred. If process variations and clock jitter are critical, then custom or hybrid topology may be preferred.

Hierarchical: This uses a tree-like structure with multiple levels of buffers to distribute the clock signal from a single source. It can achieve lower power consumption and area than a mesh based one but also suffers from a higher skew and jitter due to unequal path lengths and buffer delays. 

Mesh Network

Mesh: This uses a grid-like structure with multiple sources and cross-links to distribute the clock signal.  It can can achieve lower skew and jitter than a hierarchical topology, but it can also consume more power and area due to redundant wires and buffers.

Hybrid Tree

H-tree: This is a balanced tree structure that divides the chip into four quadrants and distributes the clock signal to each quadrant using a horizontal and a vertical branch. The H-tree topology minimizes clock skew by ensuring equal path lengths and loads for all destinations. However, it also consumes more power and area than other topologies, and it is sensitive to process variations and clock jitter.

Source Synchronous

Source synchronous: This is a topology that uses a separate clock signal for each data signal that is transmitted between different chips or systems. The clock signal is generated at the source endpoint and travels along with the data signal to the sink endpoint. The sink endpoint uses the received clock signal to sample the data signal. The source synchronous topology eliminates clock skew and reduces power consumption by avoiding global clock distribution. However, it also requires more I/O pins and introduces more clock jitter and duty cycle distortion due to transmission effects.

Fishbone: This is a variation of the H-tree topology that uses tapping points to connect local clock trees to the global clock tree. The tapping points are chosen to balance the loads and delays of each branch. The fishbone topology reduces power consumption and area overhead compared to the H-tree topology, but it also introduces more clock skew due to the mismatch between tapping points and destinations.

Here are some examples of chips that use different clock topologies:

A 10nm system-on-chip (SoC) product that uses a flexible and hybrid clock topology that combines H-tree, fishbone, and source synchronous techniques . The topology and algorithm managed to produce averagely 16.98% better global skew, 42.75% less divergence on critical clock paths and with 64.5% shorter clock balancing phase compared to a conventional ASIC methodology.

A large and complex ASIC design that uses a custom clock tree synthesis method that considers process variations and minimizes non-common part of the clock tree between launch and capture flops . The method reduces timing uncertainty and improves timing closure.

A source synchronous clock design that uses Microsemi's SmartFusion2 SoC FPGA devices . The design uses dedicated DDR I/Os to transmit data and clock signals between different chips or systems, and applies timing constraints and analysis to ensure correct functionality and performance.

References:

• Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique | IEEE Journals & Magazine | IEEE Xplore https://ieeexplore.ieee.org/document/9328752
• Clock Distribution and Balancing Methodology For Large and Complex ASIC Designs - IEEE https://ewh.ieee.org/soc/cas/dallas/documents/clock_balance_ieee_seminar04.pdf
• Source Synchronous Clock Designs: Timing Constraints and Analysis - Microsemi https://www.microsemi.com/document-portal/doc_view/129842-ac373-source-synchronous-clock-designs-timing-constraints-and-analysis-app-note