Semiconductor Test
When a pluggable transceiver fails, a technician pulls it from the faceplate and fits another. When an optical engine fails inside a co-packaged switch or accelerator, it can take the whole package with it, including a very expensive piece of silicon that was working perfectly. That one difference explains most of what is unusual about testing co-packaged optics (CPO). The industry's answer is the known good optical engine: prove the engin…
by
Murugavel Ganesan
November 12, 2026
Through-Glass Vias
Intel put glass core substrates in the headlines in September 2023 and said complete solutions would reach the market in the second half of this decade. More than three years on, a technical note from the IEEE Electronics Packaging Society, updated in November 2025, still says glass has yet to be commercialised. Both statements can be true, and the gap between them is the subject of this post. Glass solves real problems in large AI packages, b…
by
Murugavel Ganesan
November 12, 2026
SoC Design
Sooner or later, an automotive customer sends a chip team a list of requests: an FMEDA, a safety manual, a dependent failure analysis, and a statement of which ASIL the part can support. ISO 26262 sits behind that list, and it was written for road vehicle systems, not for silicon. A semiconductor team has to work out what the standard means for a block of RTL that has no vehicle attached to it yet. This post goes through what Part 5 and Part 1…
by
Murugavel Ganesan
November 11, 2026
Verification
Until recently, an EDA budget was a negotiated number that stayed put for the length of a contract. AI agents change that, because they add two bills that move with use: model tokens, and the extra tool licences those agents consume when they run simulations by the hundred. Vendors and customers are now arguing openly about both. The public debate tends to quote a single token price, and a single price is no help to a manager planning next yea…
by
Murugavel Ganesan
November 11, 2026
SoC Architecture
Hardware coherency is usually presented as a yes or no question about the whole fabric. In practice each master on a SoC gets its own answer, because a CPU cluster, a DMA engine and a neural accelerator share data in very different ways. This post is a decision guide for architects. It puts rough numbers on what hardware coherency costs in storage, traffic and latency, sets out when IO or software coherency is enough, and shows how AMBA CHI, A…
by
Murugavel Ganesan
November 10, 2026
Yield
Silicon lifecycle management, or SLM, is often sold as a simple package: sensors on the chip, a dashboard in the cloud, and a promise that failures will be seen before they happen. Some of that is established engineering, and IBM was steering voltage from on-chip timing monitors in a POWER7 prototype server by 2011. Some of it is still a hope. This post treats SLM as a method. It walks through what a working programme contains from design to f…
by
Murugavel Ganesan
November 10, 2026
